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design-verification-project

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abdo-ehab-euv / sram-controller-uvm-verification

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SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
  • Updated May 14, 2026
  • SystemVerilog

Karan-nevage / D-Flip-Flop-Design-Verification-Using-UVM

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This project demonstrates design verification of a D Flip Flop using UVM methodology. It includes driver, monitor, scoreboard, and testbench components to validate functionality, ensure correct timing, and report mismatches. A clean, modular flow highlights reusable verification practices.

systemverilog uvm design-verification uvm-verification d-flip-flop d-flipflop-uvm-verification design-verification-project
  • Updated Jan 7, 2026
  • SystemVerilog

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