FPGA-implemented RISC-V processor, evolved from single-cycle to 5-stage pipelined architecture for higher performance and timing efficiency. BRAM-based instruction memory optimizes FPGA usage. Fully FPGA-ready, general-purpose yet tailorable for any AI application, demonstrated with an ML heart rate anomaly detector for wearable AI.
machine-learning python3 embedded-systems assembly-language computer-architecture linear-regression-models digital-design rv32i semiconductor-devices fpga-programming vlsi-design rtl-design hardware-design cmos-circuits hardware-software-codesign risc-v-processor application-specific-integrated-circuits digital-design-and-computer-architecture
-
Updated
Feb 22, 2026 - Verilog