This repository contains Verilog hardware design lab assignments for Introduction to VLSI CAD course at National Cheng Kung University (NCKU), covering fundamental VLSI design concepts and CAD tools.
- Lab2: Introduction to Combinational Circuits - Basic digital circuits including ALU, FFO detector, and merge sort hardware
- Lab3: Advanced Arithmetic Circuits - Fixed-point multipliers, logarithmic interpolation, and synthesis comparison
- Lab4: Register Files and Data Paths - Register file design, image repair system, FIFO, and shooting game
- Lab5: Sequential Circuits and State Machines - Moore/Mealy FSMs, sequence detector, factorial calculator, washing machine controller
- Lab6: Cubic Interpolation - 1D image enlargement using cubic interpolation
- Lab7: Bicubic Interpolation - 2D image scaling with bicubic interpolation
Each lab folder contains detailed documentation in its own README.md file.
Navigate to the specific lab directory (e.g., Lab2/Homework/) and use the following Makefile commands:
| Situation | Command | Example |
|---|---|---|
| Simulation for ProbX | make probX |
make probA_1 |
| Dump waveform for ProbX | make nWaveX |
make nWaveA_1 |
| Open superlint for ProbX | make superlintX |
make superlintA_1 |
| Post-synthesis simulation for ProbX | make probX_syn |
make probA_1_syn |
| Delete built files | make clean |
Lab assignment spec PDFs and Synthesized results are not included in this repository due to confidentiality restrictions.