[Feature] Implement DMA support#293
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| DMA_MVIN = 0 | ||
| DMA_MVOUT = 1 |
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| external DRAM-like memory and the on-chip Scratchpad Memory (dataSPM). | ||
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| It supports two main operations: | ||
| - DMA_MVIN: DRAM -> DMA Engine -> SPM |
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Rename to DMA_INFEED and DMA_OUTFEED?
| DMA_MVOUT = 1 | ||
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| class DmaEngineRTL( Component ): |
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Would this also handle instructions/control signals delivery besides data?
| SpmDataType = mk_bits( spm_data_nbits ) | ||
| MemDataType = mk_bits( mem_data_nbits ) | ||
| # Byte mask for SPM write; 1 byte = 8 bits | ||
| SpmMaskType = mk_bits( spm_data_nbits // 8 ) |
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Define CHAR_BIT = 8 inside https://github.com/tancheng/VectorCGRA/blob/master/lib/util/common.py and use it here: // CHAR_BIT
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| # Abstract external memory interface | ||
| # Request to read from DRAM | ||
| s.mem_rd_req_val = OutPort() |
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change all mem to dram, to distinguish it from sram?
| s.spm_dma_rresp_data = InPort( SpmDataType ) | ||
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| # State machine definitions | ||
| StateType = mk_bits( 4 ) |
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4 status needs to be defined inside https://github.com/tancheng/VectorCGRA/blob/master/lib/util/common.py
| s.mem_rd_req_val = OutPort() # dma_read_request_valid | ||
| s.mem_rd_req_rdy = InPort() # dma_read_request_ready | ||
| s.mem_rd_req_addr = OutPort(DmaDramAddrType) |
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Why can't we use the RecvIfcRTL and SendIfcRTL interfaces to connect the DmaRTL?
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Related issue: coredac/CGRA-SoC#2
This PR introduces
CgraDmaRTLwhich integrates the CGRA with a DMA engine, enabling direct memory transfers between external DRAM(don't implement now) and the CGRA's dataSPM.