Digital Control System — SystemVerilog Project

This repository contains all design, simulation, and synthesis files for our Digital Control System project.
Each folder has a specific purpose to keep development organized across phases.

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Technical Implementation Details

Core Control System

• Balance Control (balance_cntrl.sv): PID controller with soft-start timer, integrator overflow protection, and velocity-based steering coordination
• PID Controller (PID.sv): Implements proportional-integral-derivative control with pitch error saturation (±512), 18-bit integrator with overflow detection, and configurable fast-simulation mode for testing
• Segway Math (SegwayMath.sv): Pipelined arithmetic for motor speed calculation, steering scaling (3/16 factor), dead-zone compensation (±168 minimum duty), and overspeed detection (>0x600 threshold)

Sensor & Communication Interfaces

• Inertial Interface (inert_intf.sv): SPI-based communication with ST iNEMO sensor, 9-state FSM for initialization and data acquisition (pitch, pitch rate, acceleration), double-flopped interrupt synchronization
• A2D Interface (A2D_Intf.sv): Round-robin 4-channel ADC sampling via SPI (left/right load cells, steering potentiometer, battery voltage), 4-state FSM with back-to-back transaction handling
• UART Receiver (Auth_blk.sv): Asynchronous serial reception with 2-FF metastability synchronization, baud rate generation (50MHz/434 = 115,200 baud), and 3-state authorization FSM

Motor Control & Safety

• Motor Driver (mtr_drv.sv): Dual H-bridge PWM control with overcurrent detection, 5-bit accumulator for fault counting, 16-cycle decay mechanism, and automatic shutdown protection
• PWM Generator (PWM11.sv): 11-bit resolution (~24.41kHz at 50MHz), non-overlapping complementary outputs with 64-count dead-time, SR-FF implementation with blanking windows
• Piezo Driver (piezo_drv.sv): Audio feedback system with frequency synthesis for battery low warnings and speed alerts

Rider Detection & Steering

• Steering Enable (steer_en.sv): Dual-threshold hysteresis logic for rider presence detection, 1.34-second confirmation timer, weight distribution analysis (sum/difference comparisons)
• State Machine (steer_en_SM.sv): 3-state FSM coordinating rider-on/rider-off transitions with timer control

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Folder Structure Overview

src/

Prototype Phase Files

• Used for early design exploration and temporary HDL/testbench prototypes.
• Place your in-progress or experimental SystemVerilog files here before they are finalized.
• Once stable and reviewed, move them to rtl/.

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rtl/

Project HDL Directory (Committed Files)

• Contains the final and reviewed SystemVerilog source files for the main project build.
• Only verified RTL modules should be stored here.
• This folder will represent the official implementation for synthesis and submission.

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tb/

Testbenches

• Contains all testbench files for module- and system-level verification.
• Each module in rtl/ should have a corresponding testbench here.
• Include simulation-specific helper tasks or utility files.

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sim/

Simulation Scripts and Results

• DO/TCL scripts for ModelSim or QuestaSim automation.
• Store waveform configuration (waves.do), transcripts, and simulation logs.
• Generated results (e.g., .wlf, .vcd) should be excluded via .gitignore.

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synthesis/

Synthesis Setup

• Contains synthesis constraint scripts, TCL files, and reports generated by tools such as Synopsys DC or Quartus.
• Keep synthesis-specific configurations here separate from RTL.

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reports/

Timing and Utilization Reports

• Final performance, area, and timing analysis results.
• Upload .txt or .pdf reports generated after synthesis or simulation.

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constraints/

FPGA or ASIC Constraints

• Pin assignment and timing constraint files.
• Example formats: .xdc, .sdc, .qsf.

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scripts/

Automation and Utility Scripts

• Python, Shell, or TCL scripts that automate workflow tasks (e.g., build automation, log parsing).

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docs/

Documentation and Design Notes

• Design diagrams, specifications, progress notes, and documentation PDFs.
• Place all reports or milestone deliverables here.

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quartus/ or design_vision/

Tool-Specific Project Files

• Each tool’s configuration or workspace files (e.g., Synopsys Design Vision or Intel Quartus projects).
• Do not mix tool-specific outputs with source files.

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Project Workflow Summary

Phase	Folder	Description
Prototype	src/	Develop and test new HDL ideas
Verified	rtl/	Finalized HDL committed for synthesis
Verification	tb/ + sim/	Testbenches and simulation results
Synthesis	synthesis/ + reports/	Tool output and metrics
Documentation	docs/	Reports, diagrams, design files

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Simulation Example (ModelSim)

cd sim
do run.do