Assign fixed PCI domain numbers to the host bridge. #124
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…enabled The issue was found when we enabled CONFIG_PM and tested edge events using libgpiod. > # gpiomon -r gpiochip0 55 > gpiomon: error waiting for events: Permission denied `gpiomon` will call irq_chip_pm_get() and then call pm_runtime_resume_and_get() if (IS_ENABLED(CONFIG_PM) && sfp->gc.irq.domain->pm_dev). pm_runtime_resume_and_get() will fail if the runtime pm of pinctrl device is disabled. As we expect the pinctrl driver can be always working and never suspend during runtime, unset sfp->gc.irq.domain->pm_dev to make sure pm_runtime_resume_and_get() won't be called when setting irq. Fixes: 447976a ("pinctrl: starfive: Add StarFive JH7110 sys controller driver") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230905122105.117000-2-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add system pm ops to save and restore pinctrl registers when suspending and resuming the driver, respectively. Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230905122105.117000-3-hal.feng@starfivetech.com Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add bindings for the PLL clock generator on the JH7110 RISC-V SoC. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add documentation to describe StarFive System Controller Registers. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add PLL clock inputs from PLL clock generator. Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
…set generator Add bindings for the System-Top-Group clock and reset generator (STGCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
…d reset generator Add bindings for the Image-Signal-Process clock and reset generator (ISPCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
…generator Add bindings for the Video-Output clock and reset generator (VOUTCRG) on the JH7110 RISC-V SoC by StarFive Ltd. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add driver for the StarFive JH7110 PLL clock controller and they work by reading and setting syscon registers. Co-developed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Modify PLL clocks source to be got from DTS or the fixed factor clocks. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add driver for the StarFive JH7110 System-Top-Group clock controller. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Co-developed-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add driver for the StarFive JH7110 Image-Signal-Process clock controller. And these clock controllers should power on and enable the clocks from SYSCRG before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add driver for the StarFive JH7110 Video-Output clock controller. And these clock controllers should power on and enable the clocks from SYSCRG first before registering. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Add new struct members and auxiliary_device_id of resets to support System-Top-Group, Image-Signal-Process and Video-Output on the StarFive JH7110 SoC. Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Link: https://lore.kernel.org/r/20230724055440.100947-1-xingyu.wu@starfivetech.com Signed-off-by: Stephen Boyd <sboyd@kernel.org>
…rate to 1.5GHz CPUfreq supports 4 cpu frequency loads on 375/500/750/1500MHz. But now PLL0 rate is 1GHz and the cpu frequency loads become 333/500/500/1000MHz in fact. So PLL0 rate should be set to 1.5GHz. Change the parent of cpu_root clock and the divider of cpu_core before the setting. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Fixes: e2c510d ("riscv: dts: starfive: Add cpu scaling for JH7110 SoC") Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Use the new PM macros for the suspend and resume functions to be automatically dropped by the compiler when CONFIG_PM or CONFIG_PM_SLEEP are disabled, without having to use #ifdef guards. This has the advantage of always compiling these functions in, independently of any Kconfig option. Thanks to that, bugs and other regressions are subsequently easier to catch. Signed-off-by: Paul Cercueil <paul@crapouillou.net> Reviewed-by: Guenter Roeck <linux@roeck-us.net> Link: https://lore.kernel.org/r/20230706082928.10869-1-paul@crapouillou.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Wim Van Sebroeck <wim@linux-watchdog.org>
Add bindings for the timer on the JH7110 RISC-V SoC by StarFive Technology Ltd. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
Add timer driver for the StarFive JH7110 SoC. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data. The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can be configured with hardware pull-up resistors to match the SOC voltage (usually 1.8V). The software can read the registers 0xA001 obtain the current LDO voltage value. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
The motorcomm phy (YT8531) supports the ability to adjust the drive strength of the rx_clk/rx_data, and the default strength may not be suitable for all boards. So add configurable options to better match the boards.(e.g. StarFive VisionFive 2) When we configure the drive strength, we need to read the current LDO voltage value to ensure that it is a legal value at that LDO voltage. Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Samin Guo <samin.guo@starfivetech.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20230804020254.291239-2-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
Add JH7110's clock initialization code to the driver. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230804020254.291239-3-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
Add documentation to describe StarFive Pulse Width Modulation controller driver. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
Add Pulse Width Modulation driver support for StarFive JH7100 and JH7110 SoC. Co-developed-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
In JH7110 SoC, the spi module needs to use "arm,primecell-periphid" to override the h/w ID value to correctly init "spi_dev", so add "primecell.yaml" as the reference file for YAML. Signed-off-by: William Qiu <william.qiu@starfivetech.com> Link: https://lore.kernel.org/r/20230724101054.25268-2-william.qiu@starfivetech.com Signed-off-by: Mark Brown <broonie@kernel.org>
Selects ARM_AMBA platform support for StarFive SoCs required by spi and crypto dma engine. Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new() which already returns void. Eventually after all drivers are converted, .remove_new() is renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Adding AES skcipher and aead support to Starfive crypto module. Skcipher modes of operation include ecb, cbc, ctr, ofb, cfb. Aead modes include ccm and gcm. v1->v2: - Add include interrupt.h to fix compile error. (Herbert) Co-developed-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Huan Feng <huan.feng@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
kzalloc() returns NULL pointer not PTR_ERR() when it fails, so replace the IS_ERR() check with NULL pointer check. Fixes: e22471c ("crypto: starfive - Add AES skcipher and aead support") Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Add StarFive JH7110 SoC USB 2.0 PHY dt-binding. Signed-off-by: Minda Chen <minda.chen@starfivetech.com> Reviewed-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Roger Quadros <rogerq@kernel.org> Link: https://lore.kernel.org/r/20230629075115.11934-2-minda.chen@starfivetech.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
Add operation on reset for Cadence MIPI-CSI2 RX Controller. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Add support for external MIPI D-PHY. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Add support for Starfive JH7110 SoC which has the cadence csi2 receiver. Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
Add the bindings documentation for Starfive JH7110 Camera Subsystem which is used for handing image sensor data. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add starfive_camss.rst file that documents the Starfive Camera Subsystem driver which is used for handing image sensor data. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add core driver for StarFive Camera Subsystem. The code parses the device platform resources and registers related devices. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add video driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add ISP driver for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Add capture driver for StarFive Camera Subsystem. It contains two video devices: capture_yuv and capture_raw. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Parse interrupt resources and register interrupt handlers. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
Register ISP sub-device and video devices for StarFive Camera Subsystem. Signed-off-by: Jack Zhu <jack.zhu@starfivetech.com>
StarFive SoCs JH7110 display system: lcd-controller bases verisilicon dc8200 IP, and hdmi bases Innosilicon IP. Add bindings for them. Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
These are mainly used internally in vs-drm, I'm not sure if the new modifiers can be used with the existing ones. If there is a problem, I will improve it further. Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
Implement drm device registration interface Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
add 2 crtcs and 8 planes in vs-drm Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
add hdmi driver as encoder and connect Signed-off-by: Keith Zhao <keith.zhao@starfivetech.com>
Add the '-@' DTC option for the starfive devices. This option populates the '__symbols__' node that contains all the necessary symbols for supporting device-tree overlays (for instance from the firmware or the bootloader) on these devices. The starfive devices allow various modules to be connected and this enables users to create out-of-tree device-tree overlays for these modules. Please note that this change does increase the size of the resulting DTB by ~20%. For example, with v6.4 increase in size is as follows: jh7100-beaglev-starlight.dtb 6192 -> 7339 jh7100-starfive-visionfive-v1.dtb 6281 -> 7428 jh7110-starfive-visionfive-2-v1.2a.dtb 11101 -> 13447 jh7110-starfive-visionfive-2-v1.3b.dtb 11101 -> 13447 Signed-off-by: Felix Moessbauer <felix.moessbauer@siemens.com> Acked-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> Acked-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Merge all StarFive dts patches together. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Merge all StarFive maintainers changes together. Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Without fixed domain numbers, Linux fails to initialize PCI: pcie-starfive 940000000.pcie: error -ENODEV: failed to get valid pcie domain pcie-starfive 9c0000000.pcie: error -ENODEV: failed to get valid pcie domain Signed-off-by: John Clark <inindev@gmail.com>
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Without fixed domain numbers, Linux fails to initialize PCI:
Fixed PCI domain numbers are found in the upstream patch submission here:
https://patchwork.kernel.org/project/linux-riscv/patch/20231031115430.113586-21-minda.chen@starfivetech.com/