Submission: Memory-Less Self-Testing FIR Filter using Vedic Mathematics

[Rajeswari-2612]

This pull request contains the final submitted notebooks for the IEEE SSCS Code-a-Chip (ISSCC 2026) project:

“Memory-Less Self-Testing FIR Filter Using Vedic Mathematics”

Overview:

• Implements a 3-tap FIR filter with integrated self-testing
• Eliminates external memory using a memory-less verification approach
• Uses Urdhva Tiryagbhyam (Vedic multiplication) for efficient computation
• Enables distributed, localized fault detection

Contents:

• Jupyter notebook with implementation and results
• Supporting documentation and dependencies

Key Features:

• Reduced area and power (no reference memory)
• Faster computation via parallel Vedic multiplication
• Improved reliability through local fault detection
• Fully reproducible using open-source tools

Tools Used:
ModelSim, Icarus Verilog, GTKWave, OpenROAD, Magic, Netgen

This submission represents the final implementation for evaluation.