Initial submission: Power Side-Channel Vulnerability in Analog IMC Arrays (Code-a-Chip VLSI 2026)

[taanayd]

📌 Overview

This pull request contains the initial submission for the IEEE SSCS Code-a-Chip (VLSI 2026) travel grant.

The work demonstrates a critical power side-channel vulnerability in analog in-memory computing (IMC) crossbar arrays, implemented and validated using the SKY130 PDK and Ngspice.

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🚀 What is included

• Main Jupyter Notebook:
  • IMC array design and simulation
  • MAC operation implementation
  • Side-channel leakage analysis
  • Noise robustness evaluation
  • Countermeasure analysis
  • Process corner validation
  • Scaling study (4×4 to 8×8)
  • Post-layout (PEX) validation

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🔬 Key Results

• Strong correlation between supply current and input Hamming weight:
  • Pearson correlation: ρ ≈ 0.9979
• Leakage persists under:
  • Noise (down to 3 dB SNR)
  • Process variations (TT, FF, SS, SF, FS)
  • Larger array sizes
  • Post-layout parasitics

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⚠️ Key Insight

This work shows that analog IMC architectures are not inherently secure, as power consumption directly leaks input information due to device-level behavior (NMOS saturation region operation).

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📂 Files Added

• IMC_SideChannel_VLSI2026_v3.ipynb
• README.md (project documentation)

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🛠️ Reproducibility

The notebook includes:

• Environment setup (SKY130 + Ngspice)
• Step-by-step execution flow
• Fully reproducible simulations

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📎 Notes

• This is the first submission of the project
• No prior commits exist for this work in the repository

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🙌 Submission Context

Submitted as part of IEEE SSCS Code-a-Chip initiative for VLSI Symposium 2026.