VLSI26: Physics-Informed Gaussian Process for CTLE Optimization#168
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fidel-makatia wants to merge 16 commits intosscs-ose:mainfrom
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VLSI26: Physics-Informed Gaussian Process for CTLE Optimization#168fidel-makatia wants to merge 16 commits intosscs-ose:mainfrom
fidel-makatia wants to merge 16 commits intosscs-ose:mainfrom
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Physics-Informed Bayesian Optimization for Analog SerDes Equalizer Design. Includes PI-GP surrogate, cross-channel transfer learning, multi-fidelity pipeline, on-chip adaptation, and data rate scaling (112G PAM4, 100G NRZ, 200G PAM4). Validated with SKY130 BSIM4 models.
- Section 20: Layout → DRC → PEX → post-layout sim using Magic VLSI + SKY130 PDK, with live extraction on Colab - Setup cell now installs volare for full processed PDK (Magic tech files, ngspice continuous models) - Section 18 PDK validation uses volare PDK with proper .option scale=1u dimension handling - Graceful fallback to pre-computed PEX values when tools unavailable - 5th contribution: physical design flow with real SKY130 layout parasitics
Focus on VLSI-relevant interconnects: - PCB/board -> die-to-die (D2D) / interposer - Backplane -> long-reach D2D - PCIe Gen6 -> UCIe Long - Board 50mm/100mm -> D2D 50mm/100mm - All scenario names updated for chiplet context
- Channel model calibrated to IEEE 802.3ck/dj reference channel insertion loss targets at 28 GHz - SpiceCTLE class: applies actual ngspice BSIM4 AC frequency response (with caching) instead of behavioral 2-pole filter - run_ctle_transient(): ngspice transient simulation with PWL input, auto-detects volare vs raw PDK - sim_link_spice(): full link sim using SPICE CTLE - SPICE transient eye diagram comparison: behavioral vs ngspice BSIM4 side-by-side for final design - All behavioral fallbacks preserved for NGSPICE=False
Section 17 (200G PAM4) now includes realistic SKY130 technology assessment: CTLE gain at 50 GHz is -2 dB, combined with 9.5 dB PAM4 penalty yields >11 dB deficit vs 112G PAM4. Added SPICE reality check code and honest framing about advanced node requirements for 802.3dj. Also includes gen_notebook.py source for reproducibility.
- Section 16: 100G NRZ → 28G NRZ (14 GBaud, Nyquist=7 GHz) Right at SKY130 CTLE peak (+4-5 dB). 14x over OpenSerDes (best published SKY130 SerDes at 2 Gbps). Includes state-of-the-art comparison table and SPICE validation. - Section 17: 200G PAM4 → 56G PAM4 (28 GBaud, Nyquist=14 GHz) CTLE still has +2-3 dB gain. NRZ vs PAM4 trade-off analysis. - Cross-rate comparison updated: 28G NRZ vs 56G PAM4 vs 112G PAM4 - All sections include SPICE reality checks at correct frequencies - CTLE fp range narrowed to 5-20 GHz (SKY130 realistic) - Added 4th channel (D2D 100mm) to both NRZ and PAM4 studies
Section 20 completely rewritten: - Full circuit layout: 3 NMOS (M1, M2 diff pair + Mt tail) with metal1 source-to-tail routing, not just a single device - Complete PEX extraction of all device + routing parasitics (~14 fF total vs 20 fF intentional load = 70% overhead) - Post-layout ngspice AC simulation using SKY130 BSIM4 with PEX lumped caps at drain, source, and tail nodes - Pre-layout vs post-layout frequency response comparison showing BW degradation from real layout parasitics - Parasitic breakdown visualization by device and routing - Layout area estimation with pie chart - Falls back to pre-computed PEX from Azure VM extraction when Magic is not available (e.g., Google Colab)
- bp_pd['cs'] is already in fF (10-300), not farads - bp_pd['w'] is already in um (5-60), not meters - bp_pd['ib'] is already in uA (200-1500), not amps - Removed erroneous 1e15/1e6 multipliers that caused absurd area values (274 trillion um² → 950 um²) - Fixed MIM cap area: cs_v/2.0 fF/um² (SKY130) - Fixed poly resistor area: 48 ohm/sq sheet resistance - Improved Miller effect multiplier on Cgd (3x) for more realistic drain parasitic allocation
- Colab badge now points to fork/branch (fidel-makatia/ ml-serdes-equalizer) instead of upstream main (which doesn't have the file yet until PR is merged) - Added fidelmakatia@tamu.edu to author info
The previous BER calculation split all values above/below each PAM4 threshold, including multiple levels in each group. This inflated std(hi/lo) and made Q-factor tiny, giving flat BER ~0.1 for all configurations. Now computes eye height at each phase point using percentile-based level separation, then converts to BER via Q = EH/(2*sigma_n). ML-Opt achieves BER < 1e-14 (PASS), while No EQ and Manual remain at ~4e-2 (FAIL).
Removed matplotlib.use('Agg') which forced non-interactive backend,
suppressing all inline plot display. Added %matplotlib inline magic
so eye diagrams, bathtub curves, and all other plots render inline
when running the notebook.
- Add schemdraw-based circuit schematic of the source-degenerated differential CTLE (Section 2.1) - Add matplotlib layout floorplan with SKY130 layer coloring - Add IEEE Member and IEEE SSCS Member to author credentials - Add schemdraw to requirements.txt Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Strip notebook to core contribution: Physics-Informed GP for CTLE optimization. Remove DFE, PAM4, PVT corners, physical layout, multi-fidelity pipeline, algorithm benchmarks, and inflated claims. Key fixes: - Fix S4P parser to handle MHZ+DB format (C4 channel was wrong) - Fix eye_width metric (was always returning 1.0) - Fix BER computation with proper symbol alignment (skip + lag sweep) - Remove DFE that was masking 51% error rate with "open" eye - Use random+TPE data collection so PI-GP advantage is visible Honest results: PI-GP R2=0.996 vs Std GP 0.967, 1.5x sample efficiency, 4.3x transfer learning speedup, B1 at 28G NRZ with BER=8e-4 (FFE+CTLE only). C4/T20 honestly shown as too lossy. 31 cells, 2372 lines (down from 47 cells, 4250 lines).
Test B1/C4/T20 at their max achievable rates with FFE+CTLE: - B1: 28 Gbps NRZ (19.2 dB loss) — EH=1.52, BER=0 - C4: 24 Gbps NRZ (26.8 dB loss) — EH=0.42, BER=8e-4 - T20: 16 Gbps NRZ (23.2 dB loss) — EH=0.98, BER=0 All real S4P data, proper BER alignment (lag up to 100), BER-penalized optimizer objective, no DFE, no dummy data.
- Add 3 IEEE 802.3 S-parameter channel files (B1, C4, T20) so the notebook can load real measured data without fallback to analytical - Add Apache 2.0 LICENSE file - Remove gen_notebook.py (build artifact, not needed by reviewers) - Add .gitignore for local runtime outputs - Fix README install command to use requirements.txt - Match README title to notebook title - Remove overclaimed contributions not demonstrated in notebook code - Remove Magic VLSI from tools table (not used)
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Summary
Physics-Informed Gaussian Process (PI-GP) for CTLE optimization — encodes closed-form device equations (pole-zero structure) into the GP feature space instead of treating the circuit as a black box.
Author: Fidel Makatia Omusilibwa, Texas A&M University
Tools Used (All Open-Source)
Test Plan
pytest --nbmake --timeout=600— passes in ~55s