VLSI26: OpenComp_FoM notebook

[wlmoi]

VLSI26: OpenComp_FoM

StrongARM vs. Double-Tail Comparator FoM Explorer

Description

This PR submits our VLSI 2026 Code-a-Chip notebook project, OpenComp_FoM.
The project provides a reproducible, notebook-driven exploration of dynamic comparator design in SKY130, focusing on architecture-level and sizing-level tradeoffs between two widely used topologies:

• StrongARM latch comparator
• Double-tail dynamic comparator

Instead of presenting a single design point, this notebook builds a full design-space analysis workflow to support objective early-stage comparator selection under performance and robustness constraints.

Technical Scope

The notebook implements the following flow end-to-end:

• Parameterized design-space generation for both topologies under a shared search space.
• PVT sweep across TT, SS, and FF corners.
• Monte Carlo robustness analysis on shortlisted candidates.
• Unified scoring based on delay, decision energy, and input-referred noise.
• Pareto-front extraction to expose non-dominated tradeoff points.
• Educational regeneration-dynamics visualization for comparator intuition.
• Structured artifact export for reproducibility and review traceability.

What’s Included

• OpenComp_FoM.ipynb
• README.md
• VLSI26/submitted_notebooks/OpenComp_FoM/LICENSE (Apache-2.0)
• VLSI26/submitted_notebooks/OpenComp_FoM/figures/
• VLSI26/submitted_notebooks/OpenComp_FoM/spice/ (StrongARM template and SPICE hooks)
• Exported artifacts in artifacts/ (CSV, JSON, PNG, GIF)

Reproducibility and Execution

• Default execution is DEMO_MODE = True for deterministic, self-contained runs.
• Notebook exports reproducible artifacts including:
  • sweep_pvt.csv, sweep_mc.csv, ranking.csv, pareto.csv
  • claim_evidence_matrix.csv, summary.json
  • pareto_fronts.png, regeneration_dynamics.gif
• A focused real-SPICE validation path is provided for high-credibility subset verification.

Key Insights

• Architecture choice is objective-dependent: StrongARM and Double-tail occupy distinct regions of the delay-energy-noise tradeoff surface.
• Unified vs. Pareto: A unified score is useful for ranking, but Pareto analysis is necessary to avoid losing high-value alternatives.
• Robustness filtering: Nominal winners are not always robust winners; PVT and Monte Carlo filtering significantly impact candidate ordering.
• Traceability: Reproducible artifact mapping (claim-to-evidence) improves transparency and reviewer confidence.
• Reusability: The methodology serves as a template for comparator-driven front-ends, such as SAR ADC design exploration.

Verification Plan

1. Run the notebook in quick mode from a clean environment.
2. Confirm generation of all expected artifacts.
3. Inspect ranking and Pareto outputs for topology tradeoff behavior.
4. Execute focused SPICE subset (with real model configurations) for hardware-backed confirmation.

Team

• William Anthony (Team Lead)
• Benedictus Kenneth Setiadi