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1. AI-enabled-pedometer-ASIC-design-RTL-to-GDS-II- AI-enabled-pedometer-ASIC-design-RTL-to-GDS-II- Public

   A 50-µW, 32-kHz Hardware-Efficient Gait Analysis Accelerator ASIC implemented in 90nm CMOS. Features Alpha-Max magnitude approximation, Wallace Tree arithmetic optimization, and a complete RTL-to-G…

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2. ASIC-Elevator-Controller ASIC-Elevator-Controller Public

   A high-reliability ASIC elevator controller featuring a hardware-level predictive scheduling algorithm. Optimized for ultra-low power and zero-skew clocking with 77% timing margin and clean physica…

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3. pedometer_180_cmosdeisign- pedometer_180_cmosdeisign- Public

   Ultra low power pedometer chip using 3-axis accelerometer

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4. tt_um_pedometer tt_um_pedometer Public

   Ultra low power pedometer chip using 3-axis accelerometer

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5. tt_um_fp_id tt_um_fp_id Public

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6. Pedometer_CAC_Submission.ipynb Pedometer_CAC_Submission.ipynb Public

   IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE)

   Jupyter Notebook