EE677 Assignment2: Netlist Simulation and Automatic Test Pattern Generation

This assignment focuses on simulating a Verilog netlist generated by Yosys using a CMOS cell library. The supported gates include:

• BUF
• NOT
• NAND
• AND
• OR
• XOR
• NOR
• DFF
• DFFSR

In addition to standard simulation, the program now includes features to sensitize faults and generate input vectors to propagate faults in the circuit. These updates enhance the tool’s capability for Automatic Test Pattern Generation (ATPG), allowing for fault detection and propagation analysis.

Features

1. Netlist Simulation: The Verilog netlist is parsed, mapping gates and wires, and simulating the circuit based on the input test cases.
2. Fault Sensitization: The tool can now sensitize a given fault in the circuit by adjusting inputs to propagate the fault.
3. Input Vector Generation: The tool determines the required input vectors that propagate a fault to the primary outputs.
4. Sequential Simulation: Supports DFF and DFFSR gates, updating state across simulation runs for sequential circuits.

Running Instructions

To run the simulation, execute the following:

python3 main.py

In main.py, update the file path as necessary. The default is:

file_path = "./test/dff_c.v"  # Modify this line for a different input file.

Or, When prompted, you can provide the path to a Verilog file or use the default file:

file_path = "./test/adder_and_or.v"  # Update with your desired file path.

Choose Between:

1. Simulation: Simulate the netlist using the given test vectors.
2. Test: Runs unit tests to verify the functionality of the ATPG and simulation components.

The output will include details on fault sensitization and the test vector required to propagate faults to primary outputs.

Each gate’s output is calculated based on its logic type (e.g., AND, OR, DFF, etc.), and the DFF/DFFSR state is updated and reused across simulation runs.

Team Members

• Aryan Tamboli
• Ayush Gaur
• Saurabh Jadhav
• Saurabh Kumar