Computer Architecture Project 1 - RISC V RV32I verilog implementation

• Abdelsalam ElTamawy - solomspd@aucegypt.edu - 900170376
• Ahmed Ibrahim - ahmeddibrahim@aucegypt.edu - 900121237
• Andrew Fahmy - andrewk.kamal@aucegypt.edu - 900170228
• Rinal Mohamed - rinalmohamed@aucegypt.edu - 900171803

This project is an implementation for the pipelined processor/datapath. It includes the five stages of the pipeline and a working forwarding unit. It also includes a data path

This working implementation includes all RV32I instructions except for CRS and FENCE instructions. It also includes all compressed "C" instructions that expand to RV32I instruction.

The datapath features a single unified memory in place of two independant memory memories designated to instructions and data.