Fixes for LoongArch LSX + fast math

.github/workflows/ci.yml

@@ -487,6 +487,12 @@ jobs:
           arch_gnu: loongarch64
           arch_deb: loong64
           distro: ubuntu-24.04
+        - extra: -fastmath
+          version: 14
+          cross: loongarch64
+          arch_gnu: loongarch64
+          arch_deb: loong64
+          distro: ubuntu-24.04
         # - version: 14
         #   cross: mips64el
         #   arch_gnu: mips64el
@@ -500,7 +506,7 @@ jobs:
         submodules: recursive
     - name: CPU Information
       run: cat /proc/cpuinfo
-    - if: ${{ matrix.distro == 'ubuntu-24.04' }}
+    - if: ${{ matrix.distro == 'ubuntu-24.04' && ( matrix.version == '15' )}}
       run:
         sudo add-apt-repository ppa:daawesomep/toolchain-backports-noble
     - name: Install APT Dependencies
@@ -527,7 +533,7 @@ jobs:
     - name: Test
       run: |
         # shellcheck disable=SC2046
-        meson test -C build --print-errorlogs --print-errorlogs $(meson test -C build --list | grep -v emul)
+        meson test -C build --print-errorlogs --print-errorlogs  # $(meson test -C build --list | grep -v emul)
 
   clang17-qemu-rvv:
     strategy:
@@ -690,6 +696,19 @@ jobs:
           distro: ubuntu-24.04
         - version: 22
           cross: loongarch64
+          extra: -fastmath
+          arch_deb: loong64
+          arch_gnu: loongarch64
+          distro: ubuntu-24.04
+        - version: 21
+          cross: loongarch64
+          extra: -fastmath
+          arch_deb: loong64
+          arch_gnu: loongarch64
+          distro: ubuntu-24.04
+        - version: 22
+          cross: loongarch64
+          extra: -fastmath
           arch_deb: loong64
           arch_gnu: loongarch64
           distro: ubuntu-24.04
@@ -728,7 +747,7 @@ jobs:
     - name: Test
       run: |
         # shellcheck disable=SC2046
-        meson test -C build --print-errorlogs --print-errorlogs $(meson test -C build --list | grep -v emul)
+        meson test -C build --print-errorlogs --print-errorlogs  # $(meson test -C build --list | grep -v emul)
 
   clang:
     strategy:

docker/cross-files/loongarch64-clang-20-fastmath-ccache.cross

@@ -0,0 +1,21 @@
+[binaries]
+c = ['ccache', 'clang-20']
+cpp = ['ccache', 'clang++-20']
+ar = 'llvm-ar-20'
+strip = 'llvm-strip-20'
+objcopy = 'llvm-objcopy-20'
+c_ld = 'lld'
+cpp_ld = 'lld'
+exe_wrapper = ['qemu-loongarch64-static', '-L', '/usr/loongarch64-linux-gnu/', '-cpu', 'la464']
+
+[properties]
+c_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+cpp_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+c_link_args = ['--target=loongarch64-linux-gnu']
+cpp_link_args = ['--target=loongarch64-linux-gnu']
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = 'la464'
+endian = 'little'

docker/cross-files/loongarch64-clang-21-fastmath-ccache.cross

@@ -0,0 +1,21 @@
+[binaries]
+c = ['ccache', 'clang-21']
+cpp = ['ccache', 'clang++-21']
+ar = 'llvm-ar-21'
+strip = 'llvm-strip-21'
+objcopy = 'llvm-objcopy-21'
+c_ld = 'lld'
+cpp_ld = 'lld'
+exe_wrapper = ['qemu-loongarch64-static', '-L', '/usr/loongarch64-linux-gnu/', '-cpu', 'la464']
+
+[properties]
+c_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+cpp_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+c_link_args = ['--target=loongarch64-linux-gnu']
+cpp_link_args = ['--target=loongarch64-linux-gnu']
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = 'la464'
+endian = 'little'

docker/cross-files/loongarch64-clang-22-fastmath-ccache.cross

@@ -0,0 +1,21 @@
+[binaries]
+c = ['ccache', 'clang-22']
+cpp = ['ccache', 'clang++-22']
+ar = 'llvm-ar-22'
+strip = 'llvm-strip-22'
+objcopy = 'llvm-objcopy-22'
+c_ld = 'lld'
+cpp_ld = 'lld'
+exe_wrapper = ['qemu-loongarch64-static', '-L', '/usr/loongarch64-linux-gnu/', '-cpu', 'la464']
+
+[properties]
+c_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+cpp_args = ['--target=loongarch64-linux-gnu', '-march=la464', '-isystem=/usr/loongarch64-linux-gnu/include', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-O3', '-ffast-math', '-Wno-nan-infinity-disabled']
+c_link_args = ['--target=loongarch64-linux-gnu']
+cpp_link_args = ['--target=loongarch64-linux-gnu']
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = 'la464'
+endian = 'little'

docker/cross-files/loongarch64-gcc-14-fastmath-ccache.cross

@@ -0,0 +1,20 @@
+[binaries]
+c = ['ccache', 'loongarch64-linux-gnu-gcc-14']
+cpp = ['ccache', 'loongarch64-linux-gnu-g++-14']
+ar = 'loongarch64-linux-gnu-gcc-ar-14'
+strip = 'loongarch64-linux-gnu-strip'
+objcopy = 'loongarch64-linux-gnu-objcopy'
+ld = 'loongarch64-linux-gnu-ld'
+exe_wrapper = ['qemu-loongarch64-static', '-L', '/usr/loongarch64-linux-gnu/', '-cpu', 'la464']
+
+[properties]
+c_args = ['-march=loongarch64', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-Ofast']
+cpp_args = ['-march=loongarch64', '-Wextra', '-Werror', '-mlsx', '-mlasx', '-Ofast']
+#c_args = ['-march=la464', '-Wextra', '-Werror']
+#cpp_args = ['-march=la464', '-Wextra', '-Werror']
+
+[host_machine]
+system = 'linux'
+cpu_family = 'loongarch64'
+cpu = 'loongarch64'
+endian = 'little'

simde/arm/neon/ext.h

@@ -53,9 +53,10 @@ simde_vext_f16(simde_float16x4_t a, simde_float16x4_t b, const int n)
       r_.sv64 = __riscv_vslideup_vx_f16m1(a_.sv64, b_.sv64, 4-n, 4);
     #else
       const size_t n_ = HEDLEY_STATIC_CAST(size_t, n);
-      for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      const size_t len = sizeof(r_.values) / sizeof(r_.values[0]);
+      for (size_t i = 0 ; i < len ; i++) {
         size_t src = i + n_;
-        r_.values[i] = (src < (sizeof(r_.values) / sizeof(r_.values[0]))) ? a_.values[src] : b_.values[src & 3];
+        r_.values[i] = (src < len) ? a_.values[src] : b_.values[src & 3];
       }
     #endif
     return simde_float16x4_from_private(r_);
@@ -500,9 +501,10 @@ simde_vextq_f16(simde_float16x8_t a, simde_float16x8_t b, const int n)
       r_.sv128 = __riscv_vslideup_vx_f16m1(a_.sv128, b_.sv128, 8-n, 8);
     #else
       const size_t n_ = HEDLEY_STATIC_CAST(size_t, n);
-      for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+      const size_t len = sizeof(r_.values) / sizeof(r_.values[0]);
+      for (size_t i = 0 ; i < len ; i++) {
         size_t src = i + n_;
-        r_.values[i] = (src < (sizeof(r_.values) / sizeof(r_.values[0]))) ? a_.values[src] : b_.values[src & 7];
+        r_.values[i] = (src < len) ? a_.values[src] : b_.values[src & 7];
       }
     #endif
     return simde_float16x8_from_private(r_);
@@ -550,7 +552,7 @@ simde_vextq_f32(simde_float32x4_t a, simde_float32x4_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 2)), HEDLEY_STATIC_CAST(int8_t, ((n) + 3))); \
       simde_float32x4_from_private(simde_vextq_f32_r_); \
     }))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_f32(a, b, n) (__extension__ ({ \
       simde_float32x4_private simde_vextq_f32_r_; \
       simde_vextq_f32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_float32x4_to_private(a).values, simde_float32x4_to_private(b).values, \
@@ -612,6 +614,11 @@ simde_vextq_f64(simde_float64x2_t a, simde_float64x2_t b, const int n)
   #define vextq_f64(a, b, n) simde_vextq_f64((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && (defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_LOONGARCH))
+HEDLEY_DIAGNOSTIC_PUSH
+SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_int8x16_t
 simde_vextq_s8(simde_int8x16_t a, simde_int8x16_t b, const int n)
@@ -654,7 +661,7 @@ simde_vextq_s8(simde_int8x16_t a, simde_int8x16_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 14)), HEDLEY_STATIC_CAST(int8_t, ((n) + 15))); \
       simde_int8x16_from_private(simde_vextq_s8_r_); \
     }))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_s8(a, b, n) (__extension__ ({ \
       simde_int8x16_private simde_vextq_s8_r_; \
       simde_vextq_s8_r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, simde_int8x16_to_private(a).values, simde_int8x16_to_private(b).values, \
@@ -712,7 +719,7 @@ simde_vextq_s16(simde_int16x8_t a, simde_int16x8_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 6)), HEDLEY_STATIC_CAST(int8_t, ((n) + 7))); \
       simde_int16x8_from_private(simde_vextq_s16_r_); \
     }))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_s16(a, b, n) (__extension__ ({ \
       simde_int16x8_private simde_vextq_s16_r_; \
       simde_vextq_s16_r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, simde_int16x8_to_private(a).values, simde_int16x8_to_private(b).values, \
@@ -764,7 +771,7 @@ simde_vextq_s32(simde_int32x4_t a, simde_int32x4_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 2)), HEDLEY_STATIC_CAST(int8_t, ((n) + 3))); \
       simde_int32x4_from_private(simde_vextq_s32_r_); \
     }))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_s32(a, b, n) (__extension__ ({ \
       simde_int32x4_private simde_vextq_s32_r_; \
       simde_vextq_s32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_int32x4_to_private(a).values, simde_int32x4_to_private(b).values, \
@@ -778,6 +785,10 @@ simde_vextq_s32(simde_int32x4_t a, simde_int32x4_t b, const int n)
   #define vextq_s32(a, b, n) simde_vextq_s32((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && (defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_LOONGARCH))
+HEDLEY_DIAGNOSTIC_POP
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_int64x2_t
 simde_vextq_s64(simde_int64x2_t a, simde_int64x2_t b, const int n)
@@ -813,7 +824,7 @@ simde_vextq_s64(simde_int64x2_t a, simde_int64x2_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 0)), HEDLEY_STATIC_CAST(int8_t, ((n) + 1))); \
       simde_int64x2_from_private(simde_vextq_s64_r_); \
     }))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_s64(a, b, n) (__extension__ ({ \
       simde_int64x2_private simde_vextq_s64_r_; \
       simde_vextq_s64_r_.values = SIMDE_SHUFFLE_VECTOR_(64, 16, simde_int64x2_to_private(a).values, simde_int64x2_to_private(b).values, \
@@ -826,6 +837,11 @@ simde_vextq_s64(simde_int64x2_t a, simde_int64x2_t b, const int n)
   #define vextq_s64(a, b, n) simde_vextq_s64((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && (defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_LOONGARCH))
+HEDLEY_DIAGNOSTIC_PUSH
+SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint8x16_t
 simde_vextq_u8(simde_uint8x16_t a, simde_uint8x16_t b, const int n)
@@ -854,7 +870,7 @@ simde_vextq_u8(simde_uint8x16_t a, simde_uint8x16_t b, const int n)
 }
 #if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
   #define simde_vextq_u8(a, b, n) simde_uint8x16_from_m128i(_mm_alignr_epi8(simde_uint8x16_to_m128i(b), simde_uint8x16_to_m128i(a), n * sizeof(uint8_t)))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_u8(a, b, n) (__extension__ ({ \
       simde_uint8x16_private simde_vextq_u8_r_; \
       simde_vextq_u8_r_.values = SIMDE_SHUFFLE_VECTOR_(8, 16, simde_uint8x16_to_private(a).values, simde_uint8x16_to_private(b).values, \
@@ -902,7 +918,7 @@ simde_vextq_u16(simde_uint16x8_t a, simde_uint16x8_t b, const int n)
 }
 #if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
   #define simde_vextq_u16(a, b, n) simde_uint16x8_from_m128i(_mm_alignr_epi8(simde_uint16x8_to_m128i(b), simde_uint16x8_to_m128i(a), n * sizeof(uint16_t)))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_u16(a, b, n) (__extension__ ({ \
       simde_uint16x8_private simde_vextq_u16_r_; \
       simde_vextq_u16_r_.values = SIMDE_SHUFFLE_VECTOR_(16, 16, simde_uint16x8_to_private(a).values, simde_uint16x8_to_private(b).values, \
@@ -912,7 +928,7 @@ simde_vextq_u16(simde_uint16x8_t a, simde_uint16x8_t b, const int n)
         HEDLEY_STATIC_CAST(int8_t, ((n) + 6)), HEDLEY_STATIC_CAST(int8_t, ((n) + 7))); \
       simde_uint16x8_from_private(simde_vextq_u16_r_); \
     }))
-#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector)
+#elif HEDLEY_HAS_BUILTIN(__builtin_shufflevector) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_u16(a, b, n) (__extension__ ({ \
     simde_uint16x8_private r_; \
     r_.values = __builtin_shufflevector( \
@@ -955,7 +971,7 @@ simde_vextq_u32(simde_uint32x4_t a, simde_uint32x4_t b, const int n)
 }
 #if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
   #define simde_vextq_u32(a, b, n) simde_uint32x4_from_m128i(_mm_alignr_epi8(simde_uint32x4_to_m128i(b), simde_uint32x4_to_m128i(a), n * sizeof(uint32_t)))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_u32(a, b, n) (__extension__ ({ \
       simde_uint32x4_private simde_vextq_u32_r_; \
       simde_vextq_u32_r_.values = SIMDE_SHUFFLE_VECTOR_(32, 16, simde_uint32x4_to_private(a).values, simde_uint32x4_to_private(b).values, \
@@ -969,6 +985,10 @@ simde_vextq_u32(simde_uint32x4_t a, simde_uint32x4_t b, const int n)
   #define vextq_u32(a, b, n) simde_vextq_u32((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && (defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_LOONGARCH))
+HEDLEY_DIAGNOSTIC_POP
+#endif
+
 SIMDE_FUNCTION_ATTRIBUTES
 simde_uint64x2_t
 simde_vextq_u64(simde_uint64x2_t a, simde_uint64x2_t b, const int n)
@@ -997,7 +1017,7 @@ simde_vextq_u64(simde_uint64x2_t a, simde_uint64x2_t b, const int n)
 }
 #if defined(SIMDE_X86_SSSE3_NATIVE) && !defined(SIMDE_BUG_GCC_SIZEOF_IMMEDIATE)
   #define simde_vextq_u64(a, b, n) simde_uint64x2_from_m128i(_mm_alignr_epi8(simde_uint64x2_to_m128i(b), simde_uint64x2_to_m128i(a), n * sizeof(uint64_t)))
-#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32)
+#elif defined(SIMDE_SHUFFLE_VECTOR_) && !defined(SIMDE_ARM_NEON_A32V7_NATIVE) && !defined(SIMDE_BUG_GCC_BAD_VEXT_REV32) && !defined(SIMDE_BUG_GCC_121064)
   #define simde_vextq_u64(a, b, n) (__extension__ ({ \
       simde_uint64x2_private simde_vextq_u64_r_; \
       simde_vextq_u64_r_.values = SIMDE_SHUFFLE_VECTOR_(64, 16, simde_uint64x2_to_private(a).values, simde_uint64x2_to_private(b).values, \
@@ -1010,8 +1030,10 @@ simde_vextq_u64(simde_uint64x2_t a, simde_uint64x2_t b, const int n)
   #define vextq_u64(a, b, n) simde_vextq_u64((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_RISCV64)
 HEDLEY_DIAGNOSTIC_PUSH
-SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIAZILED_
+SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
+#endif
 
 SIMDE_FUNCTION_ATTRIBUTES
 simde_poly8x8_t
@@ -1065,7 +1087,10 @@ simde_vext_p16(simde_poly16x4_t a, simde_poly16x4_t b, const int n)
   #define vext_p16(a, b, n) simde_vext_p16((a), (b), (n))
 #endif
 
+#if defined(SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_) && defined(HEDLEY_GCC_VERSION) && defined(SIMDE_ARCH_RISCV64)
 HEDLEY_DIAGNOSTIC_POP
+SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
+#endif
 
 SIMDE_FUNCTION_ATTRIBUTES
 simde_poly64x1_t
@@ -1106,9 +1131,10 @@ simde_vextq_p8(simde_poly8x16_t a, simde_poly8x16_t b, const int n)
       b_ = simde_poly8x16_to_private(b),
       r_ = a_;
     const size_t n_ = HEDLEY_STATIC_CAST(size_t, n);
-    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+    const size_t len = sizeof(r_.values) / sizeof(r_.values[0]);
+    for (size_t i = 0 ; i < len ; i++) {
       size_t src = i + n_;
-      r_.values[i] = (src < (sizeof(r_.values) / sizeof(r_.values[0]))) ? a_.values[src] : b_.values[src & 15];
+      r_.values[i] = (src < len) ? a_.values[src] : b_.values[src & 15];
     }
     return simde_poly8x16_from_private(r_);
   #endif
@@ -1132,9 +1158,10 @@ simde_vextq_p16(simde_poly16x8_t a, simde_poly16x8_t b, const int n)
       b_ = simde_poly16x8_to_private(b),
       r_ = a_;
     const size_t n_ = HEDLEY_STATIC_CAST(size_t, n);
-    for (size_t i = 0 ; i < (sizeof(r_.values) / sizeof(r_.values[0])) ; i++) {
+    const size_t len = sizeof(r_.values) / sizeof(r_.values[0]);
+    for (size_t i = 0 ; i < len ; i++) {
       size_t src = i + n_;
-      r_.values[i] = (src < (sizeof(r_.values) / sizeof(r_.values[0]))) ? a_.values[src] : b_.values[src & 7];
+      r_.values[i] = (src < len) ? a_.values[src] : b_.values[src & 7];
     }
     return simde_poly16x8_from_private(r_);
   #endif

simde/arm/neon/ld1_x2.h

@@ -36,7 +36,7 @@
 HEDLEY_DIAGNOSTIC_PUSH
 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
 #if HEDLEY_GCC_VERSION_CHECK(7,0,0)
-  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIAZILED_
+  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
 #endif
 SIMDE_BEGIN_DECLS_
 

simde/arm/neon/ld1_x3.h

@@ -35,7 +35,7 @@
 HEDLEY_DIAGNOSTIC_PUSH
 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
 #if HEDLEY_GCC_VERSION_CHECK(7,0,0)
-  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIAZILED_
+  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
 #endif
 SIMDE_BEGIN_DECLS_
 

simde/arm/neon/ld1_x4.h

@@ -36,7 +36,7 @@
 HEDLEY_DIAGNOSTIC_PUSH
 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
 #if HEDLEY_GCC_VERSION_CHECK(7,0,0)
-  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIAZILED_
+  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
 #endif
 SIMDE_BEGIN_DECLS_
 

simde/arm/neon/ld1q_x2.h

@@ -38,7 +38,7 @@
 HEDLEY_DIAGNOSTIC_PUSH
 SIMDE_DISABLE_UNWANTED_DIAGNOSTICS
 #if HEDLEY_GCC_VERSION_CHECK(7,0,0)
-  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIAZILED_
+  SIMDE_DIAGNOSTIC_DISABLE_MAYBE_UNINITIALIZED_
 #endif
 SIMDE_BEGIN_DECLS_