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2 parents 0c19af6 + 480c0d4 commit cbfb43eCopy full SHA for cbfb43e
logiklib/__init__.py
@@ -4,4 +4,6 @@
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def register_part_data(fpga, package_name, part_name):
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fpga.set_dataroot(
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package_name,
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- f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz", f"v{__version__}")
+ f"https://github.com/siliconcompiler/logiklib/releases/download/v{__version__}/{part_name}_cad.tar.gz",
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+ f'v{__version__}'
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+ )
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