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Merge pull request #15 from siliconcompiler/version_bump_0_2_0_rc2
Bump version number
2 parents 9c9f3df + 7c0ee70 commit 0c19af6

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logiklib/__init__.py

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__version__ = "0.1.2"
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__version__ = "0.2.0rc2"
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def register_part_data(fpga, package_name, part_name):

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