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petergrossmann21petergrossmann21
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Merge pull request #14 from siliconcompiler/download_repairs
Download repairs
2 parents 726454a + bc63135 commit 9c9f3df

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7 files changed

+65
-65
lines changed

7 files changed

+65
-65
lines changed

‎logiklib/__init__.py‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -4,4 +4,4 @@
44
def register_part_data(fpga, package_name, part_name):
55
fpga.set_dataroot(
66
package_name,
7-
f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz")
7+
f"github://siliconcompiler/logiklib/v{__version__}/{part_name}_cad.tar.gz", f"v{__version__}")

‎logiklib/zeroasic/z1000/z1000.py‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,10 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1000"):
40-
self.set_vpr_archfile('cad/z1000.xml')
41-
self.set_vpr_graphfile('cad/z1000_rr_graph.xml')
42-
self.set_yosys_config('cad/z1000_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
40+
self.set_vpr_archfile('z1000/cad/z1000.xml')
41+
self.set_vpr_graphfile('z1000/cad/z1000_rr_graph.xml')
42+
self.set_yosys_config('z1000/cad/z1000_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1000/cad/tech_flops.v')
4444

4545
# Define the macros that can be techmapped to based on the modes
4646
# that exist in the design
@@ -122,15 +122,15 @@ def __init__(self):
122122
# TODO: blackbox_options
123123

124124
with self.active_dataroot("logik-fpga-z1000"):
125-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1000_bitstream_map.json')
126-
self.set_vpr_constraintsmap('cad/z1000_constraint_map.json')
125+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1000/cad/z1000_bitstream_map.json')
126+
self.set_vpr_constraintsmap('z1000/cad/z1000_constraint_map.json')
127127

128128
self.set_vpr_channelwidth(100)
129129

130130
with self.active_dataroot("logik-fpga-z1000"):
131131
with self.active_fileset("z1000_opensta_liberty_files"):
132-
self.add_file('cad/vtr_primitives.lib')
133-
self.add_file(['cad/tech_flops.lib'])
132+
self.add_file('z1000/cad/vtr_primitives.lib')
133+
self.add_file(['z1000/cad/tech_flops.lib'])
134134
self.add_opensta_liberty_fileset()
135135

136136
self.set_vpr_router_lookahead('classic')

‎logiklib/zeroasic/z1002/z1002.py‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -37,10 +37,10 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1002"):
40-
self.set_vpr_archfile('cad/z1002.xml')
41-
self.set_vpr_graphfile('cad/z1002_rr_graph.xml')
42-
self.set_yosys_config('cad/z1002_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
40+
self.set_vpr_archfile('z1002/cad/z1002.xml')
41+
self.set_vpr_graphfile('z1002/cad/z1002_rr_graph.xml')
42+
self.set_yosys_config('z1002/cad/z1002_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1002/cad/tech_flops.v')
4444

4545
# Define the macros that can be techmapped to based on the modes
4646
# that exist in the design
@@ -122,15 +122,15 @@ def __init__(self):
122122
# TODO: blackbox_options
123123

124124
with self.active_dataroot("logik-fpga-z1002"):
125-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1002_bitstream_map.json')
126-
self.set_vpr_constraintsmap('cad/z1002_constraint_map.json')
125+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1002/cad/z1002_bitstream_map.json')
126+
self.set_vpr_constraintsmap('z1002/cad/z1002_constraint_map.json')
127127

128128
self.set_vpr_channelwidth(150)
129129

130130
with self.active_dataroot("logik-fpga-z1002"):
131131
with self.active_fileset("z1002_opensta_liberty_files"):
132-
self.add_file('cad/vtr_primitives.lib')
133-
self.add_file(['cad/tech_flops.lib'])
132+
self.add_file('z1002/cad/vtr_primitives.lib')
133+
self.add_file(['z1002/cad/tech_flops.lib'])
134134
self.add_opensta_liberty_fileset()
135135

136136
self.set_vpr_router_lookahead('classic')

‎logiklib/zeroasic/z1010/z1010.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,21 +37,21 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1010"):
40-
self.set_vpr_archfile('cad/z1010.xml')
41-
self.set_vpr_graphfile('cad/z1010_rr_graph.xml')
42-
self.set_yosys_config('cad/z1010_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
44-
self.set_yosys_memorymap(techmap='cad/tech_bram.v')
45-
self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt')
46-
self.set_yosys_dsptechmap('cad/tech_dsp.v',
40+
self.set_vpr_archfile('z1010/cad/z1010.xml')
41+
self.set_vpr_graphfile('z1010/cad/z1010_rr_graph.xml')
42+
self.set_yosys_config('z1010/cad/z1010_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1010/cad/tech_flops.v')
44+
self.set_yosys_memorymap(techmap='z1010/cad/tech_bram.v')
45+
self.set_yosys_memorymap(libmap='z1010/cad/bram_memory_map.txt')
46+
self.set_yosys_dsptechmap('z1010/cad/tech_dsp.v',
4747
options={'DSP_SIGNEDONLY': '1',
4848
'DSP_A_MAXWIDTH': '18',
4949
'DSP_B_MAXWIDTH': '18',
5050
'DSP_A_MINWIDTH': '2',
5151
'DSP_B_MINWIDTH': '2',
5252
'DSP_Y_MINWIDTH': '2',
5353
'DSP_NAME': '_dsp_block_'})
54-
self.add_yosys_macrolib('cad/tech_dsp_blackbox.v')
54+
self.add_yosys_macrolib('z1010/cad/tech_dsp_blackbox.v')
5555

5656
# Define the macros that can be techmapped to based on the modes
5757
# that exist in the design
@@ -169,15 +169,15 @@ def __init__(self):
169169
# TODO: blackbox_options
170170

171171
with self.active_dataroot("logik-fpga-z1010"):
172-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1010_bitstream_map.json')
173-
self.set_vpr_constraintsmap('cad/z1010_constraint_map.json')
172+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1010/cad/z1010_bitstream_map.json')
173+
self.set_vpr_constraintsmap('z1010/cad/z1010_constraint_map.json')
174174

175175
self.set_vpr_channelwidth(100)
176176

177177
with self.active_dataroot("logik-fpga-z1010"):
178178
with self.active_fileset("z1010_opensta_liberty_files"):
179-
self.add_file('cad/vtr_primitives.lib')
180-
self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib'])
179+
self.add_file('z1010/cad/vtr_primitives.lib')
180+
self.add_file(['z1010/cad/tech_flops.lib', 'z1010/cad/tech_dsp.lib', 'z1010/cad/tech_bram.lib'])
181181
self.add_opensta_liberty_fileset()
182182

183183
self.set_vpr_router_lookahead('classic')

‎logiklib/zeroasic/z1012/z1012.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,21 +37,21 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1012"):
40-
self.set_vpr_archfile('cad/z1012.xml')
41-
self.set_vpr_graphfile('cad/z1012_rr_graph.xml')
42-
self.set_yosys_config('cad/z1012_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
44-
self.set_yosys_memorymap(techmap='cad/tech_bram.v')
45-
self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt')
46-
self.set_yosys_dsptechmap('cad/tech_dsp.v',
40+
self.set_vpr_archfile('z1012/cad/z1012.xml')
41+
self.set_vpr_graphfile('z1012/cad/z1012_rr_graph.xml')
42+
self.set_yosys_config('z1012/cad/z1012_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1012/cad/tech_flops.v')
44+
self.set_yosys_memorymap(techmap='z1012/cad/tech_bram.v')
45+
self.set_yosys_memorymap(libmap='z1012/cad/bram_memory_map.txt')
46+
self.set_yosys_dsptechmap('z1012/cad/tech_dsp.v',
4747
options={'DSP_SIGNEDONLY': '1',
4848
'DSP_A_MAXWIDTH': '18',
4949
'DSP_B_MAXWIDTH': '18',
5050
'DSP_A_MINWIDTH': '2',
5151
'DSP_B_MINWIDTH': '2',
5252
'DSP_Y_MINWIDTH': '2',
5353
'DSP_NAME': '_dsp_block_'})
54-
self.add_yosys_macrolib('cad/tech_dsp_blackbox.v')
54+
self.add_yosys_macrolib('z1012/cad/tech_dsp_blackbox.v')
5555

5656
# Define the macros that can be techmapped to based on the modes
5757
# that exist in the design
@@ -169,15 +169,15 @@ def __init__(self):
169169
# TODO: blackbox_options
170170

171171
with self.active_dataroot("logik-fpga-z1012"):
172-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1012_bitstream_map.json')
173-
self.set_vpr_constraintsmap('cad/z1012_constraint_map.json')
172+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1012/cad/z1012_bitstream_map.json')
173+
self.set_vpr_constraintsmap('z1012/cad/z1012_constraint_map.json')
174174

175175
self.set_vpr_channelwidth(150)
176176

177177
with self.active_dataroot("logik-fpga-z1012"):
178178
with self.active_fileset("z1012_opensta_liberty_files"):
179-
self.add_file('cad/vtr_primitives.lib')
180-
self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib'])
179+
self.add_file('z1012/cad/vtr_primitives.lib')
180+
self.add_file(['z1012/cad/tech_flops.lib', 'z1012/cad/tech_dsp.lib', 'z1012/cad/tech_bram.lib'])
181181
self.add_opensta_liberty_fileset()
182182

183183
self.set_vpr_router_lookahead('classic')

‎logiklib/zeroasic/z1060/z1060.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,21 +37,21 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1060"):
40-
self.set_vpr_archfile('cad/z1060.xml')
41-
self.set_vpr_graphfile('cad/z1060_rr_graph.xml')
42-
self.set_yosys_config('cad/z1060_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
44-
self.set_yosys_memorymap(techmap='cad/tech_bram.v')
45-
self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt')
46-
self.set_yosys_dsptechmap('cad/tech_dsp.v',
40+
self.set_vpr_archfile('z1060/cad/z1060.xml')
41+
self.set_vpr_graphfile('z1060/cad/z1060_rr_graph.xml')
42+
self.set_yosys_config('z1060/cad/z1060_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1060/cad/tech_flops.v')
44+
self.set_yosys_memorymap(techmap='z1060/cad/tech_bram.v')
45+
self.set_yosys_memorymap(libmap='z1060/cad/bram_memory_map.txt')
46+
self.set_yosys_dsptechmap('z1060/cad/tech_dsp.v',
4747
options={'DSP_SIGNEDONLY': '1',
4848
'DSP_A_MAXWIDTH': '18',
4949
'DSP_B_MAXWIDTH': '18',
5050
'DSP_A_MINWIDTH': '2',
5151
'DSP_B_MINWIDTH': '2',
5252
'DSP_Y_MINWIDTH': '2',
5353
'DSP_NAME': '_dsp_block_'})
54-
self.add_yosys_macrolib('cad/tech_dsp_blackbox.v')
54+
self.add_yosys_macrolib('z1060/cad/tech_dsp_blackbox.v')
5555

5656
# Define the macros that can be techmapped to based on the modes
5757
# that exist in the design
@@ -169,15 +169,15 @@ def __init__(self):
169169
# TODO: blackbox_options
170170

171171
with self.active_dataroot("logik-fpga-z1060"):
172-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1060_bitstream_map.json')
173-
self.set_vpr_constraintsmap('cad/z1060_constraint_map.json')
172+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1060/cad/z1060_bitstream_map.json')
173+
self.set_vpr_constraintsmap('z1060/cad/z1060_constraint_map.json')
174174

175175
self.set_vpr_channelwidth(100)
176176

177177
with self.active_dataroot("logik-fpga-z1060"):
178178
with self.active_fileset("z1060_opensta_liberty_files"):
179-
self.add_file('cad/vtr_primitives.lib')
180-
self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib'])
179+
self.add_file('z1060/cad/vtr_primitives.lib')
180+
self.add_file(['z1060/cad/tech_flops.lib', 'z1060/cad/tech_dsp.lib', 'z1060/cad/tech_bram.lib'])
181181
self.add_opensta_liberty_fileset()
182182

183183
self.set_vpr_router_lookahead('classic')

‎logiklib/zeroasic/z1062/z1062.py‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -37,21 +37,21 @@ def __init__(self):
3737
self.set_vpr_clockmodel("route")
3838

3939
with self.active_dataroot("logik-fpga-z1062"):
40-
self.set_vpr_archfile('cad/z1062.xml')
41-
self.set_vpr_graphfile('cad/z1062_rr_graph.xml')
42-
self.set_yosys_config('cad/z1062_yosys_config.json')
43-
self.set_yosys_flipfloptechmap('cad/tech_flops.v')
44-
self.set_yosys_memorymap(techmap='cad/tech_bram.v')
45-
self.set_yosys_memorymap(libmap='cad/bram_memory_map.txt')
46-
self.set_yosys_dsptechmap('cad/tech_dsp.v',
40+
self.set_vpr_archfile('z1062/cad/z1062.xml')
41+
self.set_vpr_graphfile('z1062/cad/z1062_rr_graph.xml')
42+
self.set_yosys_config('z1062/cad/z1062_yosys_config.json')
43+
self.set_yosys_flipfloptechmap('z1062/cad/tech_flops.v')
44+
self.set_yosys_memorymap(techmap='z1062/cad/tech_bram.v')
45+
self.set_yosys_memorymap(libmap='z1062/cad/bram_memory_map.txt')
46+
self.set_yosys_dsptechmap('z1062/cad/tech_dsp.v',
4747
options={'DSP_SIGNEDONLY': '1',
4848
'DSP_A_MAXWIDTH': '18',
4949
'DSP_B_MAXWIDTH': '18',
5050
'DSP_A_MINWIDTH': '2',
5151
'DSP_B_MINWIDTH': '2',
5252
'DSP_Y_MINWIDTH': '2',
5353
'DSP_NAME': '_dsp_block_'})
54-
self.add_yosys_macrolib('cad/tech_dsp_blackbox.v')
54+
self.add_yosys_macrolib('z1062/cad/tech_dsp_blackbox.v')
5555

5656
# Define the macros that can be techmapped to based on the modes
5757
# that exist in the design
@@ -169,15 +169,15 @@ def __init__(self):
169169
# TODO: blackbox_options
170170

171171
with self.active_dataroot("logik-fpga-z1062"):
172-
self.set("tool", "convert_bitstream", "bitstream_map", 'cad/z1062_bitstream_map.json')
173-
self.set_vpr_constraintsmap('cad/z1062_constraint_map.json')
172+
self.set("tool", "convert_bitstream", "bitstream_map", 'z1062/cad/z1062_bitstream_map.json')
173+
self.set_vpr_constraintsmap('z1062/cad/z1062_constraint_map.json')
174174

175175
self.set_vpr_channelwidth(150)
176176

177177
with self.active_dataroot("logik-fpga-z1062"):
178178
with self.active_fileset("z1062_opensta_liberty_files"):
179-
self.add_file('cad/vtr_primitives.lib')
180-
self.add_file(['cad/tech_flops.lib', 'cad/tech_dsp.lib', 'cad/tech_bram.lib'])
179+
self.add_file('z1062/cad/vtr_primitives.lib')
180+
self.add_file(['z1062/cad/tech_flops.lib', 'z1062/cad/tech_dsp.lib', 'z1062/cad/tech_bram.lib'])
181181
self.add_opensta_liberty_fileset()
182182

183183
self.set_vpr_router_lookahead('classic')

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