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Compilation error for rust-hdl-ok-frontpanel-sys

Status: Open.

#48 In samitbasu/rust-hdl;

· loriiiiiiiii opened on May 15, 2025

Error with the simulation

Status: Open.

#47 In samitbasu/rust-hdl;

· OscarLopezCentenera opened on Apr 26, 2025

State machine that doesn't work

Status: Open.

#46 In samitbasu/rust-hdl;

· OscarLopezCentenera opened on Apr 16, 2025

Feature Request: add support for running VHDL/Verilog code alongside/within RustHDL

Status: Open.

#42 In samitbasu/rust-hdl;

· parker-research opened on May 10, 2024

Support for Sipeed Tang Nano 9K FPGA Development Board Gowin GW1NR-9 RISC-V HDMI (Tang Nano 9k)

Status: Open.

#41 In samitbasu/rust-hdl;

· Cr0a3 opened on Apr 4, 2024

How does this project works? Any papers or docs?

Status: Open.

#35 In samitbasu/rust-hdl;

· myrfy001 opened on Nov 25, 2023

Request: VHDL output

Status: Open.

#34 In samitbasu/rust-hdl;

· tschinz opened on Nov 20, 2023

Support for BeagleV-Fire

Status: Open.

#33 In samitbasu/rust-hdl;

· jimkring opened on Nov 3, 2023

Why rename?

Status: Open.

#32 In samitbasu/rust-hdl;

· alexpyattaev opened on Oct 14, 2023

Dumping BRAM Contents in Simulation

Status: Open.

#31 In samitbasu/rust-hdl;

· ThePerfectComputer opened on Oct 2, 2023

Calling Simulation::add_testbench multiple times makes the simulations interfere with each other

Status: Open.

#30 In samitbasu/rust-hdl;

· PoignardAzur opened on Jul 23, 2023

Naming a signal "output" triggers a "custom attribute panicked" error message

Status: Open.

#29 In samitbasu/rust-hdl;

· PoignardAzur opened on Jul 22, 2023