[prefetcher] Fix issue causing a race condition between cache access …#220
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medav wants to merge 1 commit intos5z:masterfrom
Open
[prefetcher] Fix issue causing a race condition between cache access …#220medav wants to merge 1 commit intos5z:masterfrom
medav wants to merge 1 commit intos5z:masterfrom
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…and invalidates When the prefetcher issues memory requests, it uses the same child lock as the given demand request. This means when the parent cache begins its transaction, it gives up this lock meaning a pending invalidate could overwrite the demand request before the response is sent back to the child cache. This causes an assert failure in the cache coherence code (coherence_ctrls.cpp:114). This fix resolves the issue by performing the demand access LAST in the prefetcher's access routine. This ensures the request always returns with a valid coherence state and does not cause the assert failure.
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…and invalidates
When the prefetcher issues memory requests, it uses the same child lock as the given
demand request. This means when the parent cache begins its transaction, it gives up
this lock meaning a pending invalidate could overwrite the demand request before the
response is sent back to the child cache. This causes an assert failure in the cache
coherence code (coherence_ctrls.cpp:114).
This fix resolves the issue by performing the demand access LAST in the prefetcher's
access routine. This ensures the request always returns with a valid coherence state
and does not cause the assert failure.