riscv-proc

Implementing single-cycle, pipelined variants of an RV32 processor in SystemVerilog.

Follows the single-cycle design and pipeline architecture outlined in the RISC-V edition of
Digital Design and Computer Architecture by David and Sarah Harris.

Along with this, a minimal SIMD implementation has been provided.
See the report on design and testing.

Files

single/core.sv - slightly modified single-cycle implementation from the book
pipeline/core.sv - pipelined implementation, modified version of another project
common.sv - modules common to single/, pipeline/
csimd.sv - common.sv, but with SIMD support while reusing components

Tools and Usage

I've used iverilog and gtkwave to compile and test
To test, modify mem.sv to read specified hexfile
See test/ for sample test files
Run the following within single/ or pipeline/

iverilog -g2012 core.sv ../csimd.sv mem.sv tb.sv -o risc_sim
vvp risc_sim
gtkwave tb.vcd

Note: single/tb.sv uses the default testbench provided in H&H, if needed swap out with pipeline/tb.sv

Supported Instructions

• Most RV32I Base Integer instr., except unsigned, U-type, and a few I-type and B-type
• mul and mulh from the RV32M Multiply Extension
  Note: these instr. execute in 1 cycle, like in some digital signal processors (not realistic for general processors).
• Basic SIMD unsigned instr. (to use SIMD, use csimd.sv in place of common.sv)
  Refer to SIMD for instruction encoding details

Type	Instructions
R-type	add, sub, slt, xor, sll, srl, or, and, mul, mulh
I-type	addi, slti, xori, slli, srli, ori, andi, lw
S-type	sw
B-type	beq
J-type	jal
SIMD	acc8, acc16, add8, add16, mul8, mul16

TODO

• Basic branch prediction
• Compatibility with RISC-V Packed extension (SIMD)
• Support for RISC-V BitManip extension (for use with SIMD)

References

• Digital Design and Computer Architecture: RISC-V Edition
• RISC-V Docs
• RISC-V Pipelined implementation
• RISC-V Reference Card
• CircuiTikz RISC-V H&H macro for design diagrams in report.pdf