A collection of high-performance hardware modules and digital design patterns implemented in SystemVerilog and Verilog. This repository focuses on efficient RTL (Register Transfer Level) design, simulation, and verification of common hardware components.
This repository contains a suite of RTL designs ranging from basic arithmetic units to complex control logic and memory structures. Each module is accompanied by a dedicated testbench and design documentation to ensure reliability and clarity.
- Synthesizable RTL: Optimized for both FPGA and ASIC synthesis.
- Verification Suites: Robust testbenches using standard Verilog/SystemVerilog methodologies.
- Comprehensive Documentation: Detailed
DESIGN.mdfor each module explaining the architecture and logic.
The repository is organized into specific modules, each containing its own rtl, tb, and documentation:
| Module | Description | Implementation |
|---|---|---|
| BCLA Adder | Block Carry Lookahead Adder for high-speed addition. | SystemVerilog |
| BCLA Comparator | Magnitude comparator based on BCLA logic. | SystemVerilog |
| Booth's Multiplier | Signed binary multiplication using Booth's algorithm. | SystemVerilog |
| Shift-Add Multiplier | Traditional sequential multiplier logic. | SystemVerilog |
| Sync FIFO | Synchronous First-In-First-Out memory buffer. | SystemVerilog |
- Hardware Description Languages:
- Simulation & Verification:
- Icarus Verilog - Open-source Verilog simulator.
- GTKWave - Fully featured waveform viewer.
Ensure you have the following tools installed:
- Icarus Verilog (
iverilog) - GTKWave
Navigate to any module directory and run the following commands:
# Compile the design and testbench
iverilog -o sim.vvp rtl/*.sv tb/*.sv
# Run simulation
vvp sim.vvp
# View waveforms
gtkwave dump.vcdThis project is licensed under the MIT License. See the LICENSE file for details.
Rickarya Das
- GitHub: @ridash2005
- LinkedIn: Rickarya Das