Physical-Layout-for-a-Two-Bit-Comparator-using-L-EDIT-IC

Physical layout of a two-bit comparator using L-EDIT IC as the final project for AVLSI course at the University of Guilan, Department of Computer Engineering, presented in Winter 2024 by Dr. Mahdi Aminian.

Gate Level Schematic of a Two Bit Comparator

Physical Layout of Circuit Implemented in L-EDIT IC

The Output Results