Skip to content

WORKAROUND: power: sequencing: qcom-wcn: skip BT devices without bt-e…#636

Open
sgaud-quic wants to merge 854 commits into
qualcomm-linux:qcom-next-stagingfrom
sgaud-quic:bt-fix
Open

WORKAROUND: power: sequencing: qcom-wcn: skip BT devices without bt-e…#636
sgaud-quic wants to merge 854 commits into
qualcomm-linux:qcom-next-stagingfrom
sgaud-quic:bt-fix

Conversation

@sgaud-quic
Copy link
Copy Markdown
Contributor

@sgaud-quic sgaud-quic commented May 30, 2026

…nable GPIO

Add a bt_gpio_required flag to the per-platform data to indicate that a chip's BT enable path requires a dedicated GPIO. Only skip matching the "bluetooth" device node when this flag is set and bt_gpio is absent.

Previously the bt_gpio check was applied unconditionally, which caused chips like WCN3990 that have no separate BT/WLAN enable pins by design to fail matching even when bt-enable GPIO is legitimately absent from the DT. Set bt_gpio_required for WCN6855 and WCN7850 which do require a dedicated BT enable GPIO.

Kuldeep Singh and others added 30 commits May 15, 2026 11:38
@Komal-Bajaj
dt-bindings: crypto: qcom,inline-crypto-engine: Document Shikra ICE
22329f7 
Document the Inline Crypto Engine (ICE) on the Shikra platform.

Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
@imrashai @Komal-Bajaj
clk: qcom: common: Register reset controller only when resets are pre…
ad7a03b 
…sent

Some clock controller descriptors do not provide any reset lines. Avoid
registering a reset controller when desc->num_resets is zero by making
the registration conditional.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@imrashai @Komal-Bajaj
clk: qcom: common: Skip NULL clock hw entries during registration
2dcb496 
Some Qualcomm clock controller descriptors may contain NULL entries in the
clk_hws array. Skip such entries when registering clock hardware to avoid
passing NULL pointers to the clock framework.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@imrashai @Komal-Bajaj
dt-bindings: clock: qcom: Add GCC LPASS clocks support for Shikra
51cfc2c 
Add GCC LPASS clocks support for Qualcomm Shikra SoC.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@imrashai @Komal-Bajaj
clk: qcom: gcc-shikra: Mark GCC LPASS clocks as critical
ac6b043 
The GCC LPASS clocks must be enabled to access audio core clock controller
registers. Hence, mark them as critical on Qualcomm Shikra SoCs.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@imrashai @Komal-Bajaj
dt-bindings: clock: qcom: Add Qualcomm Shikra Audio Core Clock Contro…
c1255bc 
…ller

Add device tree bindings for the Audio Core clock controller on Qualcomm
Shikra SoC.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@imrashai @Komal-Bajaj
clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra…
0409df3 
… SoC

Add support for Audio core clock controller on Qualcomm Shikra SoC.

Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
@kotarake @Komal-Bajaj
soc: qcom: rpmpd: Reuse sm6125 power domains for shikra
ec15f8b 
Shikra shares the same power domain topology as sm6125.
Remove the dedicated shikra_rpmpds[] and update shikra_desc
to reuse sm6125_rpmpds[] with RPM_SMD_LEVEL_TURBO_NO_CPR.

Signed-off-by: Rakesh Kota <rakesh.kota@oss.qualcomm.com>
@QuinAsura
FROMLIST: arm64: dts: qcom: Move board nodes to common DTSI
af320b7 
The display, peripherals (touchpad/touchscreen/keypad), usb and their
dependent device nodes are common to both Glymur and Mahua CRDs,
so move them from glymur-crd.dts to glymur-crd.dtsi to enable code
reuse.

Link: https://lore.kernel.org/lkml/20260326-glymur-mahua-common-nodes-v1-1-12bb26920ea4@oss.qualcomm.com/
Signed-off-by: Gopikrishna Garmidi <gopikrishna.garmidi@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@QuinAsura
FROMLIST: arm64: dts: qcom: glymur: Add ADSP and CDSP for Glymur SoC
d3dc21b 
Add remoteproc PAS loader for ADSP and CDSP with its fastrpc nodes.

Link: https://lore.kernel.org/lkml/20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com/
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@QuinAsura
FROMLIST: arm64: dts: qcom: glymur-crd: Enable ADSP and CDSP
fbc986a 
Enable ADSP and CDSP on Glymur CRD board.

Link: https://lore.kernel.org/lkml/20260325035338.1393287-1-sibi.sankar@oss.qualcomm.com/
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@QuinAsura
FROMLIST: arm64: dts: glymur: Add LPASS macro codecs and pinctrl
96a4e08 
Add LPASS macro codecs and LPASS TLMM pin controller on Qualcomm glymur.
for proper sound support.

Also add GPR(Generic Pack router) node along with
APM(Audio Process Manager) and PRM(Proxy resource
Manager) audio services.

Link: https://lore.kernel.org/lkml/20260325035338.1393287-5-sibi.sankar@oss.qualcomm.com/
Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@QuinAsura
FROMLIST: arm64: dts: qcom: glymur-crd: add Audio sound card node
2d6031d 
Add the sound card of Glymur-crd board with the routing for speakers.

Add device nodes for the sound support with WSA884x smart speakers
and playback via speakers and recording via DMIC microphones.

Link: https://lore.kernel.org/lkml/20260325035338.1393287-6-sibi.sankar@oss.qualcomm.com/
Co-developed-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Mohammad Rafi Shaik <mohammad.rafi.shaik@oss.qualcomm.com>
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@taniyadas20 @QuinAsura
FROMLIST: arm64: dts: qcom: Add support for MM clock controllers for …
106c5cf 
…Glymur

Add the device nodes for the multimedia clock controllers videocc, gpucc
and gxclkctl.

Link: https://lore.kernel.org/r/20260220-glymur_mmcc_dt_config-v1-1-e0e2f43a32af@oss.qualcomm.com
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Pradyot Kumar Nayak <pradyot.nayak@oss.qualcomm.com>
@rrnayak @QuinAsura
FROMLIST: arm64: dts: qcom: glymur: Add GPU smmu node
a22f5dd 
Add the nodes to describe the GPU SMMU node.

Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-4-f83832c3bc9a@oss.qualcomm.com/
Signed-off-by: Rajendra Nayak <rajendra.nayak@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
@akhilpo-qcom @QuinAsura
FROMLIST: arm64: dts: qcom: Add GPU support for Glymur
329c83f 
The Adreno X2 series GPU present in Glymur SoC belongs to the A8x
family. It is a new HW IP with architectural improvements as well
as different set of hw configs like GMEM, num SPs, Caches sizes etc.

Add the GPU and GMU nodes to describe this hardware.

Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-5-f83832c3bc9a@oss.qualcomm.com/
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
@quic-manafm @QuinAsura
FROMLIST: arm64: dts: qcom: glymur: Add GPU cooling
b9fa9c0 
The GPU does not throttle its speed automatically when it
reaches high temperatures. Set up GPU cooling by throttling
the GPU speed when it reaches 95°C.

Link: https://lore.kernel.org/all/20260513-glymur-gpu-dt-v4-6-f83832c3bc9a@oss.qualcomm.com/
Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
@Maccraft123 @QuinAsura
FROMLIST: dt-bindings: embedded-controller: Add Qualcomm reference de…
f79499d 
…vice EC description

Add description for the EC firmware running on Hamoa/Purwa and Glymur
reference devices.

List: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-1-702f74e495f7@oss.qualcomm.com/
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Co-developed-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
@QuinAsura
FROMLIST: platform: arm64: Add driver for EC found on Qualcomm refere…
643c24b 
…nce devices

Add Embedded controller driver support for Hamoa/Purwa/Glymur qualcomm
reference boards. It handles fan control, temperature sensors, access
to EC state changes and supports reporting suspend entry/exit to the
EC.

List: https://lore.kernel.org/lkml/20260427-add-driver-for-ec-v8-2-702f74e495f7@oss.qualcomm.com/
Co-developed-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Signed-off-by: Maya Matuszczyk <maccraft123mc@gmail.com>
Signed-off-by: Sibi Sankar <sibi.sankar@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Acked-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Akhil P Oommen <akhilpo@oss.qualcomm.com>
Co-developed-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
Signed-off-by: Anvesh Jain P <anvesh.p@oss.qualcomm.com>
@0xB0D @wenmliu
FROMLIST: phy: dphy: Add lane_positions to DPHY config struct
379e911 
Add lane_positions to the DPHY configuration struct. This data-field
represents the physical positions of the data-lanes indexed by lane number.

Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-1-c6df5599284a@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: phy: dphy: Add lane_polarities to DPHY config struct
d0dfd7a 
Pass an array of data-lane polarities from controller to PHY. A true value
means the lane polarity is inverted.

Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-2-c6df5599284a@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: phy: dphy: Add clock_lane_position to DPHY config struct
1c50697 
We need to identify which lane is the clock-lane as many different PHYs
allow for a range of lanes, potentially any of the lanes to be the clock
input lane on a PHY.

Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-3-c6df5599284a@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: phy: dphy: Add clock_lane_polarity to DPHY config struct
13b145b 
Specify the polarity of the clock lane in DPHY mode. When true this bool
means the polarity is inverted.

Link: https://lore.kernel.org/all/20260325-dphy-params-extension-v1-4-c6df5599284a@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: dt-bindings: phy: qcom: Add CSI2 C-PHY/DPHY schema
5208fd0 
Add a base schema initially compatible with x1e80100 to describe MIPI CSI2
PHY devices.

The hardware can support both CPHY, DPHY and a special split-mode DPHY. We
capture those modes as:

- PHY_QCOM_CSI2_MODE_DPHY
- PHY_QCOM_CSI2_MODE_CPHY
- PHY_QCOM_CSI2_MODE_SPLIT_DPHY

The CSIPHY devices have their own pinouts on the SoC as well as their own
individual voltage rails.

The need to model voltage rails on a per-PHY basis leads us to define
CSIPHY devices as individual nodes.

Two nice outcomes in terms of schema and DT arise from this change.

1. The ability to define on a per-PHY basis voltage rails.
2. The ability to require those voltage.

We have had a complete bodge upstream for this where a single set of
voltage rail for all CSIPHYs has been buried inside of CAMSS.

Much like the I2C bus which is dedicated to Camera sensors - the CCI bus in
CAMSS parlance, the CSIPHY devices should be individually modelled.

Link: https://lore.kernel.org/all/20260326-x1e-csi2-phy-v5-1-0c0fc7f5c01b@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: phy: qcom-mipi-csi2: Add a CSI2 MIPI DPHY driver
2bf02f7 
Add a new MIPI CSI2 driver in DPHY mode initially. The entire set of
existing CAMSS CSI PHY init sequences are imported in order to save time
and effort in later patches.

The following devices are supported in this drop:
"qcom,x1e80100-csi2-phy"

In-line with other PHY drivers the process node is included in the name.
Data-lane and clock lane positioning and polarity selection via newly
amended struct phy_configure_opts_mipi_dphy{} is supported.

The Qualcomm 3PH class of PHYs can do both DPHY and CPHY mode. For now only
DPHY is supported.

In porting some of the logic over from camss-csiphy*.c to here its also
possible to rationalise some of the code.

In particular use of regulator_bulk and clk_bulk as well as dropping the
seemingly useless and unused interrupt handler.

The PHY sequences and a lot of the logic that goes with them are well
proven in CAMSS and mature so the main thing to watch out for here is how
to get the right sequencing of regulators, clocks and register-writes.

The register init sequence table is imported verbatim from the existing
CAMSS csiphy driver. A follow-up series will rework the table to extract
the repetitive per-lane pattern into a loop.

Link: https://lore.kernel.org/all/20260326-x1e-csi2-phy-v5-2-0c0fc7f5c01b@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add optional PHY h…
98a94df 
…andle definitions

Add optional PHY handle definitions. This will allow for supporting both
legacy PHY definitions as well as supporting the optional new handle based
approach.

Drop the legacy high-level 0p8 and 1p2 supplies as required, each PHY has
its own individual rails. The old binding is still valid but with
individual nodes we define the rails in the CSIPHY sub-nodes.

Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-1-5b93415be6dd@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Add support for co…
679e06d 
…mbo-mode endpoints

Qualcomm CSI2 PHYs support a mode where two sensors may be attached to the
one CSIPHY.

When we have one endpoint we may have
- DPHY 1, 2 or 4 data lanes + 1 clock lane
- CPHY 3 wire data lane

When we have two endpoints this indicates the special fixed combo-mode.
- DPHY endpoint0 => 2+1 and endpoint1 => 1+1 data-lane/clock-lane combination.

Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-2-5b93415be6dd@linaro.org/
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: dt-bindings: media: qcom,x1e80100-camss: Describe iommu ent…
862f466 
…ries

The original iommus list included entries for ICP and BPS/IPE S1
contexts. Only the five S1 HLOS stream IDs are required by the CAMSS
ISP hardware: IFE/IFE_LITE read and write, SFE read and write, and
CDM IFE. The remaining entries serve other hardware blocks which will
be described in their own nodes as support is added.

Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-3-5b93415be6dd@linaro.org/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
@0xB0D @wenmliu
FROMLIST: media: qcom: camss: Add support to populate sub-devices
2de5b26 
Use devm_of_platform_populate() to populate subs in the tree.

Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-4-5b93415be6dd@linaro.org/
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
@0xB0D @wenmliu
FROMLIST: media: qcom: camss: Add legacy_phy flag to SoC definition s…
a2d4cea 
…tructures

Flag which SoCs have legacy - builtin PHY code. This will be useful in
subsequent patches to inform PHY bringup logic if legacy bindings are
available.

Link: https://lore.kernel.org/all/20260326-b4-linux-next-25-03-13-dtsi-x1e80100-camss-v11-5-5b93415be6dd@linaro.org/
Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org>
Tested-by: Christopher Obbard <christopher.obbard@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Loic Poulain <loic.poulain@oss.qualcomm.com>
sgaud-quic and others added 25 commits May 20, 2026 14:42
@sgaud-quic
Merge remote-tracking branch tech/storage/all into qcom-next
c74f914
@sgaud-quic
Merge remote-tracking branch tech/all/dt/qcs6490 into qcom-next
0df7217
@sgaud-quic
Merge remote-tracking branch tech/all/dt/qcs9100 into qcom-next
6f2c7b6
@sgaud-quic
Merge remote-tracking branch tech/all/dt/qcs8300 into qcom-next
de053f1
@sgaud-quic
Merge remote-tracking branch tech/all/dt/qcs615 into qcom-next
8263c88
@sgaud-quic
Merge remote-tracking branch tech/all/dt/agatti into qcom-next
fee1314
@sgaud-quic
Merge remote-tracking branch tech/all/dt/hamoa into qcom-next
818a2c1
@sgaud-quic
Merge remote-tracking branch tech/all/dt/glymur into qcom-next
07d16f9
@sgaud-quic
Merge remote-tracking branch tech/all/dt/kaanapali into qcom-next
3991694 
# Conflicts:
#	arch/arm64/boot/dts/qcom/kaanapali.dtsi
@sgaud-quic
Merge remote-tracking branch tech/all/dt/pakala into qcom-next
ed3bbd8
@sgaud-quic
Merge remote-tracking branch tech/all/config into qcom-next
9e22409
@sgaud-quic
Merge remote-tracking branch tech/overlay/dt into qcom-next
94ae194
@sgaud-quic
Merge remote-tracking branch tech/all/workaround into qcom-next
fd16fe9 
# Conflicts:
#	drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@sgaud-quic
Merge remote-tracking branch tech/mproc/all into qcom-next
6ebb080
@sgaud-quic
Merge remote-tracking branch tech/noup/debug/all into qcom-next
c43d34f
@sgaud-quic
Merge remote-tracking branch tech/hwe/unoq into qcom-next
00b54d7
@sgaud-quic
Merge remote-tracking branch early/hwe/shikra/drivers into qcom-next
a842b21 
# Conflicts:
#	Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
#	drivers/remoteproc/qcom_q6v5_pas.c
#	drivers/soc/qcom/smem.c
@sgaud-quic
Merge remote-tracking branch early/hwe/shikra/dt into qcom-next
5bf3a9f
@sgaud-quic
Add qcom-next log files for 20260520
d6c3566 
Adding merge log file and topic_SHA1 file

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
@Komal-Bajaj
Prepare qcom-next based on tag 'Linux 7.1-rc4' of https://git.kernel.…
65bde2f 
…org/pub/scm/linux/kernel/git/torvalds/linux.git

tech/bsp/clk eea3e98 11
tech/bsp/devfreq a0c2f21 6
tech/bsp/ec 643c24b 2
tech/bsp/soc-infra 20c09ce 3
tech/bsp/pinctrl 3f1acf8 1
tech/bsp/remoteproc a7b9b6d 10
tech/bus/peripherals 287f0f5 8
tech/bus/pci/all c266573 14
tech/bus/pci/phy aaf8ef1 4
tech/bus/usb/dwc 49ac8e0 2
tech/bus/usb/phy 8c7f91d 35
tech/debug/hwtracing 25c6a74 30
tech/pmic/misc ee32a8c 5
tech/mem/iommu 1fa98cb 5
tech/mm/audio/all cab3357 10
tech/mm/camss 147ae87 28
tech/mm/drm 2fbdd74 60
tech/mm/fastrpc e0ba718 9
tech/mm/phy 56ccbf4 1
tech/mm/video 8bbe314 36
tech/mm/gpu cee7794 5
tech/net/ath 850c3c0 15
tech/net/phy a3602e9 1
tech/net/bluetooth 9cca493 2
tech/pm/power 2d42c35 9
tech/pm/thermal 3f033cb 7
tech/security/crypto f030676 14
tech/security/ice 1564b82 25
tech/storage/phy cf1667f 1
tech/storage/all e254dae 1
tech/all/dt/qcs6490 58c1242 20
tech/all/dt/qcs9100 b51f0ee 18
tech/all/dt/qcs8300 ffd35fe 16
tech/all/dt/qcs615 9e2f111 9
tech/all/dt/agatti c828f10 1
tech/all/dt/hamoa 670d002 29
tech/all/dt/glymur 29aa2ab 25
tech/all/dt/kaanapali 33d3cd7 11
tech/all/dt/pakala fee7c34 8
tech/all/config ff67f6a 61
tech/overlay/dt bc66459 47
tech/all/workaround d15f5a1 15
tech/mproc/all 0aa90b7 3
tech/noup/debug/all d2b684d 25
tech/hwe/unoq b2ea57b 5
early/hwe/shikra/drivers b26f0d6 86
early/hwe/shikra/dt 919fd6c 61
@quic-manafm @sgaud-quic
FROMLIST: arm64: dts: qcom: glymur: Enable SPEL powercap driver
2fd1cb8 
The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware
based power monitoring and limiting capabilities for various power
domains including System, SoC, CPU clusters, GPU, and various other
subsystems for glymur.

Signed-off-by: Manaf Meethalavalappu Pallikunhi <manaf.pallikunhi@oss.qualcomm.com>
Link: https://patch.msgid.link/20260519-qcom_spel_driver_upstream-v1-3-75356d1b7f94@oss.qualcomm.com
@sauana @sgaud-quic
FROMLIST: arm64: dts: qcom: glymur: Configure DP endpoints for 2-lane…
aca2e0c 
… operation

Add explicit data-lanes to the MDSS DP output endpoints to enable
display port in 2 lanes configuration and disable the mode-switch
property from the USB QMP PHY node.

Signed-off-by: Saurabh Anand <saurabh.anand@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20260521120058.2966709-1-saurabh.anand@oss.qualcomm.com/
@aastpand @sgaud-quic
QCLINUX: defconfig: Enable Qualcomm SPEL driver
df3ae97 
The Qualcomm SoC Power and Electrical Limits (SPEL) provides hardware
based power monitoring and limiting capabilities for various power
domains including System, SoC, CPU clusters, GPU, and various other
subsystems. The driver integrates with the Linux powercap framework, exposing SPEL
capabilities through powercap sysfs interfaces. This allows userspace
applications and thermal management daemons to monitor energy consumption
and configure power limits for optimal power/performance balance.

Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
@sgaud-quic
Revert "firmware: qcom: scm: Allow QSEECOM on Glymur CRD"
8b93fc6 
Adding glymur-crd to the QSEECOM allowlist causes qcom_scm to fully
initialize at early boot, which sets up uefisecapp and registers EFI
variable operations. This makes efi_has_tpm2() succeed by reading the
LoaderTpm2ActivePcrBanks EFI variable, satisfying ConditionSecurity=tpm2
in systemd.

As a result, systemd activates tpm2.target which unconditionally waits
for /dev/tpm0 and /dev/tpmrm0.
systemd waits the full 90-second timeout for each of the two
TPM device units, pushing total boot time beyond 2 minutes.

Revert until TPM driver in place and /dev/tpm0 node is created.

This reverts commit 87a1698.

Signed-off-by: Salendarsingh Gaud <sgaud@qti.qualcomm.com>
@shuaz-shuai @sgaud-quic
WORKAROUND: power: sequencing: qcom-wcn: skip BT devices without bt-e…
68be752 
…nable GPIO

Add a bt_gpio_required flag to the per-platform data to indicate that
a chip's BT enable path requires a dedicated GPIO.  Only skip matching
the "bluetooth" device node when this flag is set and bt_gpio is absent.

Previously the bt_gpio check was applied unconditionally, which caused
chips like WCN3990 that have no separate BT/WLAN enable pins by design
to fail matching even when bt-enable GPIO is legitimately absent from
the DT.  Set bt_gpio_required for WCN6855 and WCN7850 which do require
a dedicated BT enable GPIO.

Signed-off-by: Shuai Zhang <shuai.zhang@oss.qualcomm.com>
@qcomlnxci
Copy link
Copy Markdown

qcomlnxci commented May 30, 2026

Test jobs on 68be752

@qcomlnxci
Copy link
Copy Markdown

qcomlnxci commented May 30, 2026

Test Matrix

Test Case glymur-crd kaanapali-mtp lemans-evk monaco-evk qcs615-ride qcs6490-rb3gen2 qcs8300-ride qcs9100-ride-r3 sm8750-mtp x1e80100-crd
BT_FW_KMD_Service ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
BT_ON_OFF ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ✅ Pass ◻️
BT_SCAN ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ✅ Pass ◻️
CPUFreq_Validation ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
CPU_affinity ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
DSP_AudioPD ⚠️ skip ◻️ ✅ Pass ✅ Pass ⚠️ skip ✅ Pass ✅ Pass ⚠️ skip ✅ Pass ◻️
Ethernet ⚠️ skip ◻️ ⚠️ skip ✅ Pass ⚠️ skip ⚠️ skip ⚠️ skip ⚠️ skip ⚠️ skip ◻️
Freq_Scaling ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
GIC ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
IPA ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
Interrupts ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
OpenCV ✅ Pass ◻️ ✅ Pass ⚠️ skip ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
PCIe ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ◻️
Probe_Failure_Check ✅ Pass ◻️ ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
RMNET ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
UFS_Validation ⚠️ skip ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
USBHost ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
WiFi_Firmware_Driver ✅ Pass ◻️ ❌ Fail ⚠️ skip ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
WiFi_OnOff ✅ Pass ◻️ ✅ Pass ❌ Fail ✅ Pass ✅ Pass ❌ Fail ✅ Pass ✅ Pass ◻️
adsp_remoteproc ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
cdsp_remoteproc ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
gpdsp_remoteproc ⚠️ skip ◻️ ✅ Pass ✅ Pass ⚠️ skip ⚠️ skip ✅ Pass ❌ Fail ⚠️ skip ◻️
hotplug ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
irq ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
kaslr ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
pinctrl ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
qcom_hwrng ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
remoteproc ❌ Fail ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
rngtest ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
shmbridge ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
smmu ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
watchdog ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
wpss_remoteproc ⚠️ skip ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ⚠️ skip ◻️

@qcomlnxci
Copy link
Copy Markdown

qcomlnxci commented May 31, 2026

Test jobs on 68be752

@qcomlnxci
Copy link
Copy Markdown

qcomlnxci commented May 31, 2026

Test Matrix

Test Case glymur-crd kaanapali-mtp lemans-evk monaco-evk qcs615-ride qcs6490-rb3gen2 qcs8300-ride qcs9100-ride-r3 sm8750-mtp x1e80100-crd
BT_FW_KMD_Service ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
BT_ON_OFF ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
BT_SCAN ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
CPUFreq_Validation ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
CPU_affinity ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
DSP_AudioPD ⚠️ skip ◻️ ✅ Pass ✅ Pass ⚠️ skip ✅ Pass ✅ Pass ⚠️ skip ✅ Pass ◻️
Ethernet ⚠️ skip ◻️ ⚠️ skip ✅ Pass ⚠️ skip ⚠️ skip ⚠️ skip ⚠️ skip ⚠️ skip ◻️
Freq_Scaling ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
GIC ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
IPA ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
Interrupts ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
OpenCV ✅ Pass ◻️ ✅ Pass ⚠️ skip ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
PCIe ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ◻️
Probe_Failure_Check ✅ Pass ◻️ ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
RMNET ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
UFS_Validation ⚠️ skip ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
USBHost ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
WiFi_Firmware_Driver ✅ Pass ◻️ ❌ Fail ⚠️ skip ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
WiFi_OnOff ✅ Pass ◻️ ✅ Pass ❌ Fail ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
adsp_remoteproc ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
cdsp_remoteproc ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
gpdsp_remoteproc ⚠️ skip ◻️ ✅ Pass ✅ Pass ⚠️ skip ⚠️ skip ✅ Pass ❌ Fail ⚠️ skip ◻️
hotplug ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
irq ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
kaslr ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
pinctrl ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
qcom_hwrng ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
remoteproc ❌ Fail ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
rngtest ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
shmbridge ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ❌ Fail ❌ Fail ❌ Fail ❌ Fail ◻️
smmu ✅ Pass ◻️ ❌ Fail ✅ Pass ❌ Fail ✅ Pass ✅ Pass ❌ Fail ✅ Pass ◻️
watchdog ✅ Pass ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ◻️
wpss_remoteproc ⚠️ skip ◻️ ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ✅ Pass ⚠️ skip ◻️

@sgaud-quic sgaud-quic force-pushed the qcom-next-staging branch from 8b93fc6 to e7ae89a Compare May 31, 2026 16:23
Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment

Reviewers

No reviews

Assignees

No one assigned

Labels

None yet

Projects

None yet

Milestone

No milestone

Development

Successfully merging this pull request may close these issues.