Enable iface clock and power domain for kodiak and monaco ice sdhc#908
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Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if power domain is enabled. Specify both power domain and the iface clock. Link: https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-1-90bbcc057361@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
Qualcomm in-line crypto engine (ICE) platform driver specifies and votes for its own resources. Before accessing ICE hardware during probe, to avoid potential unclocked register access issues (when clk_ignore_unused is not passed on the kernel command line), in addition to the 'core' clock the 'iface' clock should also be turned on by the driver. This can only be done if power domain is enabled. Specify both power domain and the iface clock. Link: https://lore.kernel.org/linux-arm-msm/20260409-ice_emmc_clock_addition-v2-2-90bbcc057361@oss.qualcomm.com/ Signed-off-by: Kuldeep Singh <kuldeep.singh@oss.qualcomm.com>
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Previously, ice used to exists jointly with ufs/mmc driver and not a
standalone driver.
With recent efforts of making ice as separate module after decoupling
from ufs driver. Update sdhc ice kodiak/moanco DT nodes to adapt power
domain and iface clock to probe successfully.
The patchset is motivation to fix ice mmc where ice ufs is fixed with
below series.
https://lore.kernel.org/linux-arm-msm/20260323-qcom_ice_power_and_clk_vote-v4-0-e36044bbdfe9@oss.qualcomm.com/T/#m5da5dd7a18318583b23ffeb42fa07ef1438042d5
Testing: