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Merged
Komal-Bajaj merged 2 commits into from
Apr 10, 2026
Merged

Add eMMC support for Shikra #904

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c626dbe
arm64: dts: qcom: Add eMMC support for shikra SoC
Apr 7, 2026
2455e7e
arm64: dts: qcom: Enable eMMC for shikra EVK
Apr 7, 2026
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17 changes: 17 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
chassis-type = "embedded";

aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
};

Expand All @@ -21,6 +22,22 @@
};
};

&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;

pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";

non-removable;
supports-cqe;
no-sdio;
no-sd;

status = "okay";
};

&uart0 {
status = "okay";
};
17 changes: 17 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
chassis-type = "embedded";

aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
};

Expand All @@ -21,6 +22,22 @@
};
};

&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;

pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";

non-removable;
supports-cqe;
no-sdio;
no-sd;

status = "okay";
};

&uart0 {
status = "okay";
};
17 changes: 17 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -13,6 +13,7 @@
chassis-type = "embedded";

aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
};

Expand All @@ -21,6 +22,22 @@
};
};

&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;

pinctrl-0 = <&sdc1_state_on>;
pinctrl-1 = <&sdc1_state_off>;
pinctrl-names = "default", "sleep";

non-removable;
supports-cqe;
no-sdio;
no-sd;

status = "okay";
};

&uart0 {
status = "okay";
};
116 changes: 116 additions & 0 deletions arch/arm64/boot/dts/qcom/shikra.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -5,6 +5,7 @@

#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
Expand Down Expand Up @@ -364,6 +365,56 @@
drive-strength = <2>;
bias-disable;
};

sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <6>;
bias-disable;
};

cmd-pins {
pins = "sdc1_cmd";
drive-strength = <6>;
bias-pull-up;
};

data-pins {
pins = "sdc1_data";
drive-strength = <6>;
bias-pull-up;
};

rclk-pins {
pins = "sdc1_rclk";
bias-pull-down;
};
};

sdc1_state_off: sdc1-off-state {
clk-pins {
pins = "sdc1_clk";
drive-strength = <2>;
bias-bus-hold;
};

cmd-pins {
pins = "sdc1_cmd";
drive-strength = <2>;
bias-bus-hold;
};

data-pins {
pins = "sdc1_data";
drive-strength = <2>;
bias-bus-hold;
};

rclk-pins {
pins = "sdc1_rclk";
bias-bus-hold;
};
};
};

mem_noc: interconnect@d00000 {
Expand Down Expand Up @@ -482,6 +533,71 @@
reg = <0x0 0x04690000 0x0 0x14000>;
};

sdhc_1: mmc@4744000 {
compatible = "qcom,shikra-sdhci", "qcom,sdhci-msm-v5";

reg = <0x0 0x04744000 0x0 0x1000>,
<0x0 0x04745000 0x0 0x1000>;
reg-names = "hc",
"cqhci";

iommus = <&apps_smmu 0xc0 0x0>;

interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "hc_irq",
"pwr_irq";

clocks = <&gcc GCC_SDCC1_AHB_CLK>,
<&gcc GCC_SDCC1_APPS_CLK>,
<&rpmcc RPM_SMD_XO_CLK_SRC>;
clock-names = "iface",
"core",
"xo";

interconnects = <&system_noc MASTER_SDCC_1 QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI_CH0 QCOM_ICC_TAG_ALWAYS>,
<&mem_noc MASTER_AMPSS_M0 QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_SDCC_1 QCOM_ICC_TAG_ACTIVE_ONLY>;
interconnect-names = "sdhc-ddr",
"cpu-sdhc";

power-domains = <&rpmpd RPMHPD_CX>;
operating-points-v2 = <&sdhc1_opp_table>;

qcom,dll-config = <0x000f642c>;
qcom,ddr-config = <0x80040868>;

bus-width = <8>;

mmc-ddr-1_8v;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;

resets = <&gcc GCC_SDCC1_BCR>;

status = "disabled";

sdhc1_opp_table: opp-table-1 {
compatible = "operating-points-v2";

opp-100000000 {
opp-hz = /bits/ 64 <100000000>;
required-opps = <&rpmpd_opp_low_svs>;
opp-peak-kBps = <250000 133320>;
opp-avg-kBps = <104000 0>;
};

opp-384000000 {
opp-hz = /bits/ 64 <384000000>;
required-opps = <&rpmpd_opp_nom>;
opp-peak-kBps = <800000 300000>;
opp-avg-kBps = <400000 0>;
};
};
};

adreno_smmu: iommu@59a0000 {
compatible = "qcom,shikra-smmu-500", "qcom,smmu-500", "arm,mmu-500";
reg = <0x0 0x059a0000 0x0 0x10000>;
Expand Down