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FROMLIST: drm/bridge: add support for lontium lt8713sx bridge driver #483

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@quic-vishsain quic-vishsain commented Dec 29, 2025 •
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Used linux/sizes.h header for size definitions.
Used linux/crc8.h for CRC calculation
Added Basic drm_bridge changes to support corresponding ports handling in dt

abelvesa and others added 28 commits December 17, 2025 15:51
@abelvesa @riteshk-quic
FROMLIST: dt-bindings: phy: qcom-edp: Add missing clock for X Elite
775dd43 
On X Elite platform, the eDP PHY uses one more clock called ref.

The current X Elite devices supported upstream work fine without this
clock, because the boot firmware leaves this clock enabled. But we should
not rely on that. Also, even though this change breaks the ABI, it is
needed in order to make the driver disables this clock along with the
other ones, for a proper bring-down of the entire PHY.

So attach the this ref clock to the PHY.

Cc: stable@vger.kernel.org # v6.10
Fixes: 5d56078 ("dt-bindings: phy: qcom-edp: Add X1E80100 PHY compatibles")
Link:https://lore.kernel.org/all/20251030-phy-qcom-edp-add-missing-refclk-v5-1-fce8c76f855a@linaro.org/
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
@abelvesa @riteshk-quic
FROMLIST: phy: qcom: edp: Make the number of clocks flexible
dc4e00f 
On X Elite, the DP PHY needs another clock called ref, while all other
platforms do not.

The current X Elite devices supported upstream work fine without this
clock, because the boot firmware leaves this clock enabled. But we should
not rely on that. Also, even though this change breaks the ABI, it is
needed in order to make the driver disables this clock along with the
other ones, for a proper bring-down of the entire PHY.

So in order to handle these clocks on different platforms, make the driver
get all the clocks regardless of how many there are provided.

Cc: stable@vger.kernel.org # v6.10
Fixes: db83c10 ("phy: qcom: edp: Add v6 specific ops and X1E80100 platform support")
Link:https://lore.kernel.org/all/20251030-phy-qcom-edp-add-missing-refclk-v5-2-fce8c76f855a@linaro.org/
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
@riteshk-quic
FROMLIST: dt-bindings: phy: qcom-edp: Add eDP ref clk for sa8775p
18da99c 
When the initial contribution of eDP PHY for sa8775p was done,
eDP reference clock voting was missed. It worked fine at that
time because the clock was already enabled by the UFS PHY driver.

After commit 77d2fa5 ("scsi: ufs: qcom : Refactor
phy_power_on/off calls"), eDP reference clock started getting
turned off, leading to the following PHY power-on failure:

phy phy-aec2a00.phy.10: phy poweron failed --> -110

To fix this, explicit voting for the eDP reference clock is
required. This patch adds the eDP reference clock for sa8775p
eDP PHY and updates the corresponding example node.

Link:https://lore.kernel.org/all/20251104114327.27842-2-riteshk@qti.qualcomm.com/
Signed-off-by: Ritesh Kumar <quic_riteshk@quicinc.com>
@Xin-ANX @riteshk-quic
FROMLIST: drm/bridge: anx7625: Fix EDID block size at drm_edid_alloc(…
e849d0f 
…) calling

Since DRM validates the all of EDID blocks, allocates drm_edid data
structure based on the actually block count returned by the sink
monitor at drm_edid_alloc() calling.

Fixes: 7c585f9 ("drm/bridge: anx7625: use struct drm_edid more")

Signed-off-by: Xin Ji <xji@analogixsemi.com>
Link: https://lore.kernel.org/all/20250808064613.2623732-1-xji@analogixsemi.com/

Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
@riteshk-quic
FROMLIST: dt-bindings: phy: Add QMP USB3+DP PHY for QCS615
12b7563 
Add device tree binding documentation for the Qualcomm QMP USB3+DP PHY
on QCS615 Platform. This PHY supports both USB3 and DP functionality
over USB-C, with PHY mode switching capability. It does not support
combo mode.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-1-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Rename USB-specific ops to prepare for…
2e670e1 
… DP support

To support following DisplayPort (DP) mode over the Type-C PHY, rename
USB-specific functions and ops to clearly separate them from common or
DP-related logic.

This is a preparatory cleanup to enable USB + DP dual mode.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-2-dc5edaac6c2b@oss.qualcomm.com/
Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add DP-related fields for USB/DP switc…
f2e4880 
…hable PHY

Extend qmp_usbc_offsets and qmp_phy_cfg with DP-specific fields,
including register offsets, init tables, and callback hooks. Also
update qmp_usbc struct to track DP-related resources and state.
This enables support for USB/DP switchable Type-C PHYs that operate
in either mode.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-3-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add regulator init_load support
6ea05cd 
QMP USBC PHY drivers previously did not set init_load_uA for regulators,
which could result in incorrect vote levels. This patch introduces
regulator definitions with proper init_load_uA values based on each
chip's power grid design.

QCS615 USB3 PHY was previously reusing qcm2290_usb3phy_cfg, but its
regulator requirements differ. A new qcs615_usb3phy_cfg is added to
reflect the correct settings.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-4-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Move reset config into PHY cfg
1622d32 
The original reset list only works for USB-only PHYs. USB3DP PHYs require
different reset names such as "dp_phy", so they need a separate list.

Moving reset configuration into qmp_phy_cfg allows per-PHY customization
without adding special-case logic in DT parsing. The legacy DT path keeps
using the old hardcoded list, while non-legacy paths use cfg->reset_list.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-5-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: add DP link and vco_div clocks for DP PHY
c1a4fb9 
USB3DP PHY requires link and vco_div clocks when operating in DP mode.
Extend qmp_usbc_register_clocks and the clock provider logic to register
these clocks along with the existing pipe clock, to support both USB and
DP configurations.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-6-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Move USB-only init to usb_power_on
35fb8d4 
The current implementation programs USB-specific registers in
qmp_usbc_com_init(), which is shared by both USB and DP modes. This
causes unnecessary configuration when the PHY is used for DP.

Move USB-only register setup from com_init to qmp_usbc_usb_power_on,
so it runs only for USB mode.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-7-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add TCSR parsing and PHY mode setting
20882a2 
Extend TCSR parsing to read optional dp_phy_mode_reg and add
qmp_usbc_set_phy_mode() to switch between USB and DP modes when
supported.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-8-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add DP PHY ops for USB/DP switchable T…
22fbca8 
…ype-C PHYs

Define qmp_usbc_dp_phy_ops struct to support DP mode on USB/DP
switchable PHYs.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-9-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add USB/DP exclude handling
b8f4cc2 
When both USB and DP PHY modes are enabled simultaneously on the same
QMP USBC PHY, it can lead to hardware misconfiguration and undefined
behavior. This happens because the PHY resources are not designed to
operate in both modes at the same time.

To prevent this, introduce a mutual exclusion check between USB and DP
PHY modes.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-10-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp: Add DP v2 PHY register definitions
58538fa 
Add dedicated headers for DP v2 PHY, including QSERDES COM and TX/RX
register definitions.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-11-dc5edaac6c2b@oss.qualcomm.com/
@riteshk-quic
FROMLIST: phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mo…
cc9396f 
…de support

Add QCS615-specific configuration for USB/DP PHY, including DP init
routines, voltage swing tables, and platform data. Add compatible
"qcs615-qmp-usb3-dp-phy".

Note: SW_PORTSELECT handling for orientation flip is not implemented
due to QCS615 fixed-orientation design and non-standard lane mapping.

Signed-off-by: Xiangxu Yin <xiangxu.yin@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20250926-add-displayport-support-for-qcs615-platform-v7-12-dc5edaac6c2b@oss.qualcomm.com/
@Mani-chandana167 @riteshk-quic
FROMLIST: drm/msm/dp: Update msm_dp_controller IDs for sa8775p
93c5d83 
The Qualcomm SA8775P platform comes with 2 DisplayPort controllers
for each mdss. Update controller id for DPTX0 and DPTX1 of mdss1.

Fixes: dcb380d ("drm/msm/dp: Add DisplayPort controller for SA8775P")
Signed-off-by: Mani Chandana Ballary Kuntumalla <quic_mkuntuma@quicinc.com>
Link: https://lore.kernel.org/all/20251125105622.1755651-2-quic_mkuntuma@quicinc.com/
@riteshk-quic
FROMLIST: drm/panel: Set sufficient voltage for panel nt37801
4445fb8 
The NT37801 Sepc V1.0 chapter "5.7.1 Power On Sequence" states
VDDI=1.65V~1.95V, so set sufficient voltage for panel nt37801.

Signed-off-by: Yongxing Mou <yongxing.mou@oss.qualcomm.com>
Signed-off-by: Yuanjie Yang <yuanjie.yang@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20251023080609.1212-2-yuanjie.yang@oss.qualcomm.com/#r
Signed-off-by: Yash Gupta <quic_ygupt@quicinc.com>
@riteshk-quic
FROMLIST: drm/bridge: add support for lontium lt8713sx bridge driver
6336cd7 
The lt8713sx is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter,
with three configurable DP1.4/HDMI2.0/DP++ output interfaces and
audio output interface.

Driver is required for firmware upgrade in the bridge chip.

Co-developed-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20251118-lt8713sx-bridge-driver-v2-2-25ad49280a11@oss.qualcomm.com/
@riteshk-quic
FROMLIST: dt-bindings: bridge: lt8713sx: Add bindings
ee8f627 
Add bindings for lt8713sx bridge.

Co-developed-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20251118-lt8713sx-bridge-driver-v2-1-25ad49280a11@oss.qualcomm.com/
@quic-botlagun @riteshk-quic
FROMLIST: drm/bridge: lt9611uxc: Increase EDID wait time from 500ms t…
f1c59ad 
…o 1000ms

EDID interrupt was coming 600-650 ms after HPD interrupt, resulting
into EDID read timeout and default resolution of 1024x768 on display.

Signed-off-by: Gopi Botlagunta <venkata.botlagunta@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20251121-hdmibridge-v1-1-14c63890f362@oss.qualcomm.com/
@riteshk-quic
FROMLIST: dt-bindings: display: msm: document DSI controller and phy …
73797e2 
…on QCS8300

Document DSI controller and phy on QCS8300 platform.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Link: https://lore.kernel.org/all/20251125013302.3835909-4-quic_amakhija@quicinc.com/

Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
@riteshk-quic
FROMLIST: dt-bindings: msm: dsi-controller-main: document the QCS8300…
36e1149 
… DSI CTRL

Document the DSI CTRL on the QCS8300 Platform.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Link: https://lore.kernel.org/all/20251125013302.3835909-3-quic_amakhija@quicinc.com/

Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
@riteshk-quic
FROMLIST: dt-bindings: display: msm-dsi-phy-7nm: document the QCS8300…
7bd5d2d 
… DSI PHY

Document the DSI PHY on the QCS8300 Platform.

Signed-off-by: Ayushi Makhija <quic_amakhija@quicinc.com>
Link: https://lore.kernel.org/all/20251125013302.3835909-2-quic_amakhija@quicinc.com/

Signed-off-by: Arpit Saini <arpisain@qti.qualcomm.com>
@lumag @riteshk-quic
FROMLIST: drm/msm/dpu: enable virtual planes by default
22c3c04 
Turn on the switch and use virtual planes by default, enhancing
utilisation of the display pipelines. It is still possible to use legacy
implementation by using `msm.dpu_use_virtual_planes=false` kernel boot
parameter.

Link:https://lore.kernel.org/all/20250514-dpu-enable-virt-planes-v1-1-bf5ba0088007@oss.qualcomm.com/
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
@riteshk-quic
FROMLIST: drm/msm/disp/dpu: add merge3d support for sc7280
6e85255 
Add support for the merge3d block on sc7280 which will allow
merge of streams coming from two layer mixers routed to single
non DSC interface. This change helps to support larger buffer
width which exceeds max_linewidth of 2400.

Link:https://lore.kernel.org/all/20251124-merge3d-sc7280-v1-1-798d94211626@oss.qualcomm.com/
Fixes: 591e34a ("drm/msm/disp/dpu1: add support for display for SC7280 target")
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
@riteshk-quic
FROMLIST: drm/bridge: lt9611uxc: extend mode valid checks
28a9a90 
Currently valid mode checks are only for hdisplay and vdisplay,
add htotal and vtotal to filter only specific modes.

Link:https://lore.kernel.org/lkml/20251126-lt9611uxc-modes-v2-1-34bf9b351921@oss.qualcomm.com/
Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com>
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
@riteshk-quic
FROMLIST: drm/bridge: lt9611uxc: add support for 4K@30 resolution
8a0d1c0 
Add 3840x2160@30 mode in lt9611uxc modes to add support for
4K@30 resolution.

Link:https://lore.kernel.org/r/20251126-lt9611uxc-4k30-v2-1-3de0ea58c24e@oss.qualcomm.com
Signed-off-by: Nilesh Laad <nilesh.laad@oss.qualcomm.com>
Signed-off-by: Mahadevan P <mahadevan.p@oss.qualcomm.com>
@quic-vishsain quic-vishsain changed the base branch from main to tech/mm/drm December 29, 2025 08:21
@quic-vishsain quic-vishsain marked this pull request as ready for review December 29, 2025 08:25
@quic-vishsain
FROMLIST: drm/bridge: add support for lontium lt8713sx bridge driver
e8f877c 
The lt8713sx is a Type-C/DP1.4 to Type-C/DP1.4/HDMI2.0 converter,
with three configurable DP1.4/HDMI2.0/DP++ output interfaces and
audio output interface.

Driver is required for firmware upgrade in the bridge chip.

Co-developed-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Prahlad Valluru <vvalluru@qti.qualcomm.com>
Signed-off-by: Vishnu Saini <vishnu.saini@oss.qualcomm.com>
Link: https://lore.kernel.org/all/20251228-lt8713sx-bridge-driver-v3-2-9169fbef0e5b@oss.qualcomm.com/
@quic-vishsain quic-vishsain marked this pull request as draft December 30, 2025 07:06
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7 participants

@quic-vishsain @abelvesa @riteshk-quic @Xin-ANX @Mani-chandana167 @quic-botlagun @lumag