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22 changes: 11 additions & 11 deletions Bender.lock
Original file line number Diff line number Diff line change
Expand Up @@ -10,16 +10,16 @@ packages:
revision: 06410c36819924e32db2afa428d244dbdbcd5d4e
version: null
source:
Git: https://github.com/colluca/axi
Git: https://github.com/colluca/axi.git
dependencies:
- common_cells
- common_verification
- tech_cells_generic
axi_riscv_atomics:
revision: 430838a10a9bdf1e381d4fcb33907428f3273420
version: 0.6.0
revision: 0ac3a78fe342c5a5b9b10bff49d58897f773059e
version: 0.8.2
source:
Git: https://github.com/pulp-platform/axi_riscv_atomics
Git: https://github.com/pulp-platform/axi_riscv_atomics.git
dependencies:
- axi
- common_cells
Expand Down Expand Up @@ -56,7 +56,7 @@ packages:
Git: https://github.com/pulp-platform/common_verification.git
dependencies: []
fpnew:
revision: a8e0cba6dd50f357ece73c2c955d96efc3c6c315
revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
version: null
source:
Git: https://github.com/pulp-platform/cvfpu.git
Expand Down Expand Up @@ -91,8 +91,8 @@ packages:
- common_cells
- common_verification
register_interface:
revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
version: 0.4.5
revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
version: 0.4.7
source:
Git: https://github.com/pulp-platform/register_interface.git
dependencies:
Expand All @@ -104,13 +104,13 @@ packages:
revision: 358f90110220adf7a083f8b65d157e836d706236
version: 0.8.1
source:
Git: https://github.com/pulp-platform/riscv-dbg
Git: https://github.com/pulp-platform/riscv-dbg.git
dependencies:
- common_cells
- tech_cells_generic
scm:
revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
version: 1.2.0
revision: 1976c7efb4979271eee2abe262fde0f9a20e2557
version: 1.2.1
source:
Git: https://github.com/pulp-platform/scm.git
dependencies:
Expand All @@ -119,6 +119,6 @@ packages:
revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
version: 0.2.13
source:
Git: https://github.com/pulp-platform/tech_cells_generic
Git: https://github.com/pulp-platform/tech_cells_generic.git
dependencies:
- common_verification
18 changes: 9 additions & 9 deletions Bender.yml
Original file line number Diff line number Diff line change
Expand Up @@ -19,15 +19,15 @@ package:
- Matheus Cavalcante <matheusd@iis.ee.ethz.ch>

dependencies:
axi: { git: https://github.com/colluca/axi, rev: multicast }
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics, version: 0.6.0 }
common_cells: { git: https://github.com/pulp-platform/common_cells, rev: snitch }
apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.2 }
FPnew: { git: https://github.com/pulp-platform/cvfpu.git, rev: pulp-v0.1.3 }
tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic, version: 0.2.13 }
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg, version: 0.8.0 }
cluster_icache: { git: https://github.com/pulp-platform/cluster_icache.git, version: 0.3.0 }
idma: { git: https://github.com/pulp-platform/iDMA.git, version: 0.6.5 }
axi: { git: https://github.com/colluca/axi.git, rev: multicast }
axi_riscv_atomics: { git: https://github.com/pulp-platform/axi_riscv_atomics.git, version: 0.8.2 }
common_cells: { git: https://github.com/pulp-platform/common_cells.git, rev: snitch }
apb: { git: https://github.com/pulp-platform/apb.git, version: 0.2.2 }
FPnew: { git: https://github.com/pulp-platform/cvfpu.git, rev: pulp-v0.2.3 }
tech_cells_generic: { git: https://github.com/pulp-platform/tech_cells_generic.git, version: 0.2.13 }
riscv-dbg: { git: https://github.com/pulp-platform/riscv-dbg.git, version: 0.8.1 }
cluster_icache: { git: https://github.com/pulp-platform/cluster_icache.git, version: 0.3.0 }
idma: { git: https://github.com/pulp-platform/iDMA.git, version: 0.6.5 }

export_include_dirs:
- hw/reqrsp_interface/include
Expand Down
2 changes: 1 addition & 1 deletion target/asic/.gitignore
Original file line number Diff line number Diff line change
@@ -1,4 +1,4 @@
out/
reports/
tmp/
*.log
*.log
2 changes: 1 addition & 1 deletion target/asic/yosys/scripts/abc-opt.script
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,7 @@ echo "Opt+mapping Iterations..."
&opt_iter; &map_iter;
&opt_iter; &map_iter;
&put


topo
stime
Expand Down
2 changes: 1 addition & 1 deletion target/asic/yosys/scripts/filter_output.awk
Original file line number Diff line number Diff line change
Expand Up @@ -36,4 +36,4 @@ capture {
gsub(/\<Warning\>/, YELLOW "Warning" RESET)
gsub(/\<Error\>/, RED "Error" RESET)
print
}
}
2 changes: 1 addition & 1 deletion target/asic/yosys/scripts/init_tech.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -43,4 +43,4 @@ set tech_cells_args [concat {*}$tech_cells_args_list]
# read library files
foreach file $lib_list {
yosys read_liberty -lib "$file"
}
}
1 change: 0 additions & 1 deletion target/asic/yosys/scripts/techmap_latch_sg13g2.v
Original file line number Diff line number Diff line change
Expand Up @@ -24,4 +24,3 @@ module \$_DLATCH_N_ (D, E, Q);
.Q (Q)
);
endmodule

4 changes: 2 additions & 2 deletions target/asic/yosys/scripts/yosys_common.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -30,7 +30,7 @@ proc envVarValid {var_name} {
}

# If the ENVVAR is valid use it, otherwise use fallback
foreach var [dict keys $variables] {
foreach var [dict keys $variables] {
set values [dict get $variables $var]
set env_var [lindex $values 0]
set fallback [lindex $values 1]
Expand All @@ -56,4 +56,4 @@ proc processAbcScript {abc_script} {
flush $abc_out
close $abc_out
return $abc_out_path
}
}
3 changes: 1 addition & 2 deletions target/asic/yosys/scripts/yosys_synthesis.tcl
Original file line number Diff line number Diff line change
Expand Up @@ -72,7 +72,7 @@ yosys opt_expr
yosys opt -noff
yosys fsm
yosys tee -q -o "${rep_dir}/${top_design}_initial_opt.rpt" stat
yosys wreduce
yosys wreduce
yosys peepopt
yosys opt_clean
yosys opt -full
Expand Down Expand Up @@ -160,4 +160,3 @@ yosys tee -q -o "${rep_dir}/${top_design}_area_logic.rpt" stat -top $top_design

# final netlist
yosys write_verilog -noattr -noexpr -nohex -nodec ${out_dir}/${top_design}_yosys.v

6 changes: 5 additions & 1 deletion target/asic/yosys/yosys.mk
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,10 @@ $(eval $(call sn_gen_rtl_prerequisites,$(SN_YOSYS_RTL_PREREQ_FILE),$(SN_YOSYS_TM

$(SN_YOSYS_FILELIST): $(SN_BENDER_LOCK) $(SN_BENDER_YML)
$(SN_BENDER) script flist-plus $(SN_YOSYS_BENDER_FLAGS) > $@
# At the moment we need to filter out `axi_riscv_atomics` from synthesis
# since they cause elaboration issues. They are not used in the design,
# but only in the testbench, which might be the issue here.
sed -i '/axi_riscv_atomics/d' $@

# Synthesize netlist using Yosys
$(SN_YOSYS_NETLIST) $(SN_YOSYS_NETLIST_DEBUG) &: $(SN_YOSYS_FILELIST) $(SN_YOSYS_RTL_PREREQ_FILE) | $(SN_YOSYS_OUT) $(SN_YOSYS_TMP) $(SN_YOSYS_REPORTS)
Expand All @@ -68,7 +72,7 @@ yosys: $(SN_YOSYS_NETLIST)
clean-yosys:
rm -rf $(SN_YOSYS_OUT)
rm -rf $(SN_YOSYS_TMP)
rm -rf $(SN_YOSYS_REPORTS)
rm -rf $(SN_YOSYS_REPORTS)
rm -f $(SN_YOSYS_DIR)/$(SN_YOSYS_TOP_MODULE).log

clean: clean-yosys
Expand Down