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[HW] cva6: Increase AXI data width #91

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[HW] cva6: Increase AXI data width #91

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481e25a
ara_soc: Widen Ariane's AXI interconnect
niwis Nov 11, 2021
221f536
ara_system: Update Ariane's parameter list
niwis Nov 11, 2021
d862334
cva6: Bump parametrised AXI data width
niwis Nov 18, 2021
44debde
[cva6] Update cache size patch
suehtamacv Nov 18, 2021
33e0353
[ci] :memo: Add the benchmark results as an artifact
suehtamacv Nov 18, 2021
dce059e
fixme! Remove SELRANGE warnings from the verilated Ara
suehtamacv Nov 18, 2021
1f01177
cva6: Update reference and drop FPU update
niwis Nov 19, 2021
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1 change: 0 additions & 1 deletion .github/workflows/ci.yml
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Original file line number Diff line number Diff line change
Expand Up @@ -554,4 +554,3 @@ jobs:
compile-ara-${{ matrix.ara_config }}
compile-apps-${{ matrix.ara_config }}
compile-riscv-tests-${{ matrix.ara_config }}
benchmark-${{ matrix.ara_config }}
1 change: 1 addition & 0 deletions hardware/Makefile
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Expand Up @@ -158,6 +158,7 @@ $(veril_library)/V$(veril_top): $(config_file) Makefile ../Bender.yml $(shell fi
-Wno-UNSIGNED \
-Wno-WIDTH \
-Wno-WIDTHCONCAT \
-Wno-SELRANGE \
--hierarchical \
tb/verilator/waiver.vlt \
--Mdir $(veril_library) \
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2 changes: 1 addition & 1 deletion hardware/deps/cva6
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Submodule cva6 updated 25 files
+2 −2 include/ariane_pkg.sv
+29 −5 src/ariane.sv
+18 −14 src/axi_adapter.sv
+26 −13 src/axi_shim.sv
+3 −7 src/cache_subsystem/cache_ctrl.sv
+27 −12 src/cache_subsystem/cva6_icache_axi_wrapper.sv
+26 −13 src/cache_subsystem/miss_handler.sv
+34 −14 src/cache_subsystem/std_cache_subsystem.sv
+19 −9 src/cache_subsystem/std_nbdcache.sv
+1 −1 src/cache_subsystem/std_no_dcache.sv
+58 −26 src/cache_subsystem/wt_axi_adapter.sv
+18 −4 src/cache_subsystem/wt_cache_subsystem.sv
+2 −0 src/cache_subsystem/wt_dcache.sv
+9 −1 src/cache_subsystem/wt_dcache_mem.sv
+1 −1 src/csr_regfile.sv
+6 −6 tb/common/tb_dcache_pkg.sv
+30 −1 tb/tb_wb_dcache/hdl/tb.sv
+1 −0 tb/tb_wb_dcache/tb.list
+7 −0 tb/tb_wt_axi_dcache/.gitignore
+45 −0 tb/tb_wt_axi_dcache/Makefile
+920 −0 tb/tb_wt_axi_dcache/hdl/tb.sv
+232 −0 tb/tb_wt_axi_dcache/hdl/tb_amoport.sv
+42 −0 tb/tb_wt_axi_dcache/tb.list
+349 −0 tb/tb_wt_axi_dcache/wave.do
+2 −1 tb/tb_wt_dcache/tb.list
4 changes: 2 additions & 2 deletions hardware/patches/0002-cva6-cache-size.patch
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Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
diff --git a/include/ariane_pkg.sv b/include/ariane_pkg.sv
index 78ab0bf..5a70ccd 100644
index adc497e..f90c12e 100644
--- a/include/ariane_pkg.sv
+++ b/include/ariane_pkg.sv
@@ -457,14 +457,14 @@ package ariane_pkg;
Expand All @@ -11,7 +11,7 @@ index 78ab0bf..5a70ccd 100644
localparam int unsigned ICACHE_SET_ASSOC = 4; // Must be between 4 to 64
localparam int unsigned ICACHE_INDEX_WIDTH = $clog2(CONFIG_L1I_SIZE / ICACHE_SET_ASSOC); // in bit, contains also offset width
localparam int unsigned ICACHE_TAG_WIDTH = riscv::PLEN-ICACHE_INDEX_WIDTH; // in bit
localparam int unsigned ICACHE_LINE_WIDTH = 256; // in bit
localparam int unsigned ICACHE_LINE_WIDTH = 512; // in bit
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@mp-17 mp-17 Nov 29, 2021

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Do we need wider I$ lines as well?

// D$
- localparam int unsigned CONFIG_L1D_SIZE = 32*1024;
- localparam int unsigned DCACHE_SET_ASSOC = 8; // Must be between 4 to 64
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@mp-17 mp-17 Nov 29, 2021

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Okay, this should be true by default, now

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66 changes: 37 additions & 29 deletions hardware/src/ara_soc.sv
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Expand Up @@ -76,8 +76,12 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
// AXI //
///////////

// Peripheral AXI port data width
localparam AxiPeriphDataWidth = 64;
localparam AxiPeriphStrbWidth = AxiPeriphDataWidth / 8;

// Ariane's AXI port data width
localparam AxiNarrowDataWidth = 64;
localparam AxiNarrowDataWidth = ariane_pkg::DCACHE_LINE_WIDTH;
localparam AxiNarrowStrbWidth = AxiNarrowDataWidth / 8;
// Ara's AXI port data width
localparam AxiWideDataWidth = AxiDataWidth;
Expand All @@ -87,6 +91,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
localparam AxiCoreIdWidth = AxiSocIdWidth - 1;

// Internal types
typedef logic [AxiPeriphDataWidth-1:0] axi_periph_data_t;
typedef logic [AxiPeriphStrbWidth-1:0] axi_periph_strb_t;
typedef logic [AxiNarrowDataWidth-1:0] axi_narrow_data_t;
typedef logic [AxiNarrowStrbWidth-1:0] axi_narrow_strb_t;
typedef logic [AxiSocIdWidth-1:0] axi_soc_id_t;
Expand All @@ -99,17 +105,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
axi_user_t)
`AXI_TYPEDEF_ALL(soc_narrow, axi_addr_t, axi_soc_id_t, axi_narrow_data_t, axi_narrow_strb_t,
axi_user_t)
`AXI_TYPEDEF_ALL(soc_periph, axi_addr_t, axi_soc_id_t, axi_periph_data_t, axi_periph_strb_t,
axi_user_t)
`AXI_TYPEDEF_ALL(soc_wide, axi_addr_t, axi_soc_id_t, axi_data_t, axi_strb_t, axi_user_t)
`AXI_LITE_TYPEDEF_ALL(soc_narrow_lite, axi_addr_t, axi_narrow_data_t, axi_narrow_strb_t)
`AXI_LITE_TYPEDEF_ALL(soc_periph_lite, axi_addr_t, axi_periph_data_t, axi_periph_strb_t)

// Buses
system_req_t system_axi_req;
system_resp_t system_axi_resp;

soc_wide_req_t [NrAXISlaves-1:0] periph_wide_axi_req;
soc_wide_resp_t [NrAXISlaves-1:0] periph_wide_axi_resp;
soc_narrow_req_t [NrAXISlaves-1:0] periph_narrow_axi_req;
soc_narrow_resp_t [NrAXISlaves-1:0] periph_narrow_axi_resp;
soc_periph_req_t [NrAXISlaves-1:0] periph_narrow_axi_req;
soc_periph_resp_t [NrAXISlaves-1:0] periph_narrow_axi_resp;

////////////////
// Crossbar //
Expand Down Expand Up @@ -244,8 +252,8 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(

axi2apb_64_32 #(
.AXI4_ADDRESS_WIDTH(AxiAddrWidth ),
.AXI4_RDATA_WIDTH (AxiNarrowDataWidth),
.AXI4_WDATA_WIDTH (AxiNarrowDataWidth),
.AXI4_RDATA_WIDTH (AxiPeriphDataWidth),
.AXI4_WDATA_WIDTH (AxiPeriphDataWidth),
.AXI4_ID_WIDTH (AxiSocIdWidth ),
.AXI4_USER_WIDTH (AxiUserWidth ),
.BUFF_DEPTH_SLAVE (2 ),
Expand Down Expand Up @@ -310,19 +318,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(

axi_dw_converter #(
.AxiSlvPortDataWidth(AxiWideDataWidth ),
.AxiMstPortDataWidth(AxiNarrowDataWidth ),
.AxiMstPortDataWidth(AxiPeriphDataWidth ),
.AxiAddrWidth (AxiAddrWidth ),
.AxiIdWidth (AxiSocIdWidth ),
.AxiMaxReads (2 ),
.ar_chan_t (soc_wide_ar_chan_t ),
.mst_r_chan_t (soc_narrow_r_chan_t ),
.mst_r_chan_t (soc_periph_r_chan_t ),
.slv_r_chan_t (soc_wide_r_chan_t ),
.aw_chan_t (soc_narrow_aw_chan_t ),
.aw_chan_t (soc_periph_aw_chan_t ),
.b_chan_t (soc_wide_b_chan_t ),
.mst_w_chan_t (soc_narrow_w_chan_t ),
.mst_w_chan_t (soc_periph_w_chan_t ),
.slv_w_chan_t (soc_wide_w_chan_t ),
.axi_mst_req_t (soc_narrow_req_t ),
.axi_mst_resp_t (soc_narrow_resp_t ),
.axi_mst_req_t (soc_periph_req_t ),
.axi_mst_resp_t (soc_periph_resp_t ),
.axi_slv_req_t (soc_wide_req_t ),
.axi_slv_resp_t (soc_wide_resp_t )
) i_axi_slave_uart_dwc (
Expand All @@ -338,21 +346,21 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
// Control registers //
/////////////////////////

soc_narrow_lite_req_t axi_lite_ctrl_registers_req;
soc_narrow_lite_resp_t axi_lite_ctrl_registers_resp;
soc_periph_lite_req_t axi_lite_ctrl_registers_req;
soc_periph_lite_resp_t axi_lite_ctrl_registers_resp;

axi_to_axi_lite #(
.AxiAddrWidth (AxiAddrWidth ),
.AxiDataWidth (AxiNarrowDataWidth ),
.AxiDataWidth (AxiPeriphDataWidth ),
.AxiIdWidth (AxiSocIdWidth ),
.AxiUserWidth (AxiUserWidth ),
.AxiMaxReadTxns (1 ),
.AxiMaxWriteTxns(1 ),
.FallThrough (1'b0 ),
.full_req_t (soc_narrow_req_t ),
.full_resp_t (soc_narrow_resp_t ),
.lite_req_t (soc_narrow_lite_req_t ),
.lite_resp_t (soc_narrow_lite_resp_t)
.full_req_t (soc_periph_req_t ),
.full_resp_t (soc_periph_resp_t ),
.lite_req_t (soc_periph_lite_req_t ),
.lite_resp_t (soc_periph_lite_resp_t)
) i_axi_to_axi_lite (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand All @@ -366,10 +374,10 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(
ctrl_registers #(
.DRAMBaseAddr (DRAMBase ),
.DRAMLength (DRAMLength ),
.DataWidth (AxiNarrowDataWidth ),
.DataWidth (AxiPeriphDataWidth ),
.AddrWidth (AxiAddrWidth ),
.axi_lite_req_t (soc_narrow_lite_req_t ),
.axi_lite_resp_t(soc_narrow_lite_resp_t)
.axi_lite_req_t (soc_periph_lite_req_t ),
.axi_lite_resp_t(soc_periph_lite_resp_t)
) i_ctrl_registers (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand All @@ -382,19 +390,19 @@ module ara_soc import axi_pkg::*; import ara_pkg::*; #(

axi_dw_converter #(
.AxiSlvPortDataWidth(AxiWideDataWidth ),
.AxiMstPortDataWidth(AxiNarrowDataWidth ),
.AxiMstPortDataWidth(AxiPeriphDataWidth ),
.AxiAddrWidth (AxiAddrWidth ),
.AxiIdWidth (AxiSocIdWidth ),
.AxiMaxReads (2 ),
.ar_chan_t (soc_wide_ar_chan_t ),
.mst_r_chan_t (soc_narrow_r_chan_t ),
.mst_r_chan_t (soc_periph_r_chan_t ),
.slv_r_chan_t (soc_wide_r_chan_t ),
.aw_chan_t (soc_narrow_aw_chan_t),
.b_chan_t (soc_narrow_b_chan_t ),
.mst_w_chan_t (soc_narrow_w_chan_t ),
.aw_chan_t (soc_periph_aw_chan_t),
.b_chan_t (soc_periph_b_chan_t ),
.mst_w_chan_t (soc_periph_w_chan_t ),
.slv_w_chan_t (soc_wide_w_chan_t ),
.axi_mst_req_t (soc_narrow_req_t ),
.axi_mst_resp_t (soc_narrow_resp_t ),
.axi_mst_req_t (soc_periph_req_t ),
.axi_mst_resp_t (soc_periph_resp_t ),
.axi_slv_req_t (soc_wide_req_t ),
.axi_slv_resp_t (soc_wide_resp_t )
) i_axi_slave_ctrl_dwc (
Expand Down
11 changes: 10 additions & 1 deletion hardware/src/ara_system.sv
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Expand Up @@ -84,7 +84,16 @@ module ara_system import axi_pkg::*; import ara_pkg::*; #(
logic inval_ready;

ariane #(
.ArianeCfg(ArianeCfg)
.ArianeCfg (ArianeCfg ),
.AxiAddrWidth (AxiAddrWidth ),
.AxiDataWidth (AxiNarrowDataWidth ),
.AxiIdWidth (AxiIdWidth ),
.AxiUserWidth (ariane_axi::UserWidth),
.axi_ar_chan_t (ariane_axi_ar_t ),
.axi_aw_chan_t (ariane_axi_aw_t ),
.axi_w_chan_t (ariane_axi_w_t ),
.axi_req_t (ariane_axi_req_t ),
.axi_rsp_t (ariane_axi_resp_t )
) i_ariane (
.clk_i (clk_i ),
.rst_ni (rst_ni ),
Expand Down