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Merged
Navaneeth-KunhiPurayil merged 3 commits into from
Nov 25, 2025
Merged

Fix/vzext #432

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0b3d6df
[hardware] Fix emul check for src operand for vector integer extension
Navaneeth-KunhiPurayil Nov 20, 2025
1a03831
[CHANGELOG] Update Changelog
Navaneeth-KunhiPurayil Nov 20, 2025
90d29c6
[hardware] Fix check for valid dst operand
Navaneeth-KunhiPurayil Nov 22, 2025
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1 change: 1 addition & 0 deletions CHANGELOG.md
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Original file line number Diff line number Diff line change
Expand Up @@ -53,6 +53,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
- Pass CVA6Cfg to serial divider in Ara
- Force cheshire's sim scripts re-generation
- Fix u-boot to support RVV-linux
- Fixed src emul check for vector integer extension operation

### Added

Expand Down
18 changes: 18 additions & 0 deletions apps/riscv-tests/isa/rv64uv/vsext.c
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Expand Up @@ -91,6 +91,23 @@ void TEST_CASE6(void) {
VCMP_U64(12, v2, 0, 2, 0, -4, 0, 6, 0, -8, 0, -2, 0, 4, 0, -6, 0, 8);
}

void TEST_CASE7(void) {
VSET(16, e16, m2);
VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vsext.vf2 v2, v1");
VCMP_U16(13, v2, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);

VSET(16, e32, m4);
VLOAD_8(v3, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vsext.vf4 v4, v3");
VCMP_U32(14, v4, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);

VSET(16, e64, m8);
VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vsext.vf8 v8, v1");
VCMP_U64(15, v8, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
}

int main(void) {
INIT_CHECK();
enable_vec();
Expand All @@ -101,6 +118,7 @@ int main(void) {
TEST_CASE4();
TEST_CASE5();
TEST_CASE6();
TEST_CASE7();

EXIT_CHECK();
}
21 changes: 21 additions & 0 deletions apps/riscv-tests/isa/rv64uv/vzext.c
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Expand Up @@ -100,6 +100,26 @@ void TEST_CASE6(void) {
VCMP_U64(12, v2, 0, 2, 0, 252, 0, 6, 0, 248, 0, 254, 0, 4, 0, 250, 0, 8);
}

void TEST_CASE7(void) {
VSET(16, e16, m2);
VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vzext.vf2 v2, v1");
VCMP_U16(13, v2, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
8);

VSET(16, e32, m4);
VLOAD_8(v3, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vzext.vf4 v4, v3");
VCMP_U32(14, v4, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
8);

VSET(16, e64, m8);
VLOAD_8(v1, 1, 2, -3, -4, 5, 6, -7, -8, -1, -2, 3, 4, -5, -6, 7, 8);
asm volatile("vzext.vf8 v8, v1");
VCMP_U64(15, v8, 1, 2, 253, 252, 5, 6, 249, 248, 255, 254, 3, 4, 251, 250, 7,
8);
}

int main(void) {
INIT_CHECK();
enable_vec();
Expand All @@ -110,6 +130,7 @@ int main(void) {
TEST_CASE4();
TEST_CASE5();
TEST_CASE6();
TEST_CASE7();

EXIT_CHECK();
}
61 changes: 43 additions & 18 deletions hardware/src/ara_dispatcher.sv
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Expand Up @@ -110,6 +110,19 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
endcase
endfunction : next_lmul

// Calculates prev(lmul)
function automatic vlmul_e prev_lmul(vlmul_e lmul);
unique case (lmul)
LMUL_1_4: prev_lmul = LMUL_1_8;
LMUL_1_2: prev_lmul = LMUL_1_4;
LMUL_1 : prev_lmul = LMUL_1_2;
LMUL_2 : prev_lmul = LMUL_1;
LMUL_4 : prev_lmul = LMUL_2;
LMUL_8 : prev_lmul = LMUL_4;
default : prev_lmul = LMUL_RSVD;
endcase
endfunction : prev_lmul

// Calculates prev(prev(ew))
function automatic vew_e prev_prev_ew(vew_e ew);
unique case (ew)
Expand Down Expand Up @@ -1649,6 +1662,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionZExt8;
ara_req.eew_vs2 = eew_q[insn.varith_type.rs2];
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(prev_lmul(prev_lmul(csr_vtype_q.vlmul)));

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW64) ||
Expand All @@ -1659,6 +1674,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionSExt8;
ara_req.eew_vs2 = eew_q[insn.varith_type.rs2];
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(prev_lmul(prev_lmul(csr_vtype_q.vlmul)));

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW64) ||
Expand All @@ -1669,6 +1686,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionZExt4;
ara_req.eew_vs2 = prev_prev_ew(csr_vtype_q.vsew);
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(prev_lmul(csr_vtype_q.vlmul));

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW32) ||
Expand All @@ -1678,6 +1697,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionSExt4;
ara_req.eew_vs2 = prev_prev_ew(csr_vtype_q.vsew);
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(prev_lmul(csr_vtype_q.vlmul));

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW32) ||
Expand All @@ -1687,6 +1708,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionZExt2;
ara_req.eew_vs2 = csr_vtype_q.vsew.prev();
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(csr_vtype_q.vlmul);

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW16) || int'(csr_vtype_q.vlmul) inside {LMUL_1_8})
Expand All @@ -1696,6 +1719,8 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
ara_req.conversion_vs2 = OpQueueConversionSExt2;
ara_req.eew_vs2 = csr_vtype_q.vsew.prev();
ara_req.cvt_resize = CVT_WIDE;
ara_req.emul = csr_vtype_q.vlmul;
lmul_vs2 = prev_lmul(csr_vtype_q.vlmul);

// Invalid conversion
if (int'(csr_vtype_q.vsew) < int'(EW16) || int'(csr_vtype_q.vlmul) inside {LMUL_1_8})
Expand Down Expand Up @@ -1872,15 +1897,15 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
default:;
endcase
unique case (lmul_vs2)
LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs2;
default:;
endcase
unique case (lmul_vs1)
LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_2: if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs1;
LMUL_4: if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs1;
LMUL_8: if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs1;
default:;
endcase
end
Expand Down Expand Up @@ -2114,9 +2139,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
default:;
endcase
unique case (lmul_vs2)
LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_2: if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_4: if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_8: if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs2;
default:;
endcase
end
Expand Down Expand Up @@ -2532,16 +2557,16 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
default:;
endcase
unique case (lmul_vs2)
LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_RSVD: illegal_insn = 1'b1;
default:;
endcase
unique case (lmul_vs1)
LMUL_2 : if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_4 : if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_8 : if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs1;
LMUL_2 : if ((insn.varith_type.rs1 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs1;
LMUL_4 : if ((insn.varith_type.rs1 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs1;
LMUL_8 : if ((insn.varith_type.rs1 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs1;
LMUL_RSVD: illegal_insn = 1'b1;
default:;
endcase
Expand Down Expand Up @@ -2826,9 +2851,9 @@ module ara_dispatcher import ara_pkg::*; import rvv_pkg::*; #(
default:;
endcase
unique case (lmul_vs2)
LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn = ara_req.use_vs2;
LMUL_2 : if ((insn.varith_type.rs2 & 5'b00001) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_4 : if ((insn.varith_type.rs2 & 5'b00011) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_8 : if ((insn.varith_type.rs2 & 5'b00111) != 5'b00000) illegal_insn |= ara_req.use_vs2;
LMUL_RSVD: illegal_insn = 1'b1;
default:;
endcase
Expand Down
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