Unclock improvments and simulator reset during start

mips-lib/src/components/mips_reg_file.rs

@@ -162,7 +162,7 @@ impl Component for RegFile {
         Ok(())
     }
 
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         if let Some(last_op) = self.history.borrow_mut().pop() {
             let mut regs = self.registers.borrow_mut();
             if regs[last_op.addr as usize] != last_op.data {

mips-lib/src/components/physical_mem.rs

@@ -7,7 +7,7 @@ use std::{
     path::PathBuf,
 };
 use syncrim::{
-    common::{Component, Ports},
+    common::{Component, Ports, Simulator},
     signal::Id,
 };
 
@@ -60,7 +60,7 @@ impl Component for PhysicalMem {
         self
     }
 
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         *self.cycle.borrow_mut() -= 1;
         if let Some(op) = self.history.borrow_mut().remove(&*self.cycle.borrow()) {
             self.mem.borrow_mut().revert(op);

riscv/src/components/clic.rs

@@ -684,7 +684,7 @@ impl Component for CLIC {
         Ok(())
     }
 
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         // TODO: Add super-clic stack ops
         let mut entry = self.history.borrow_mut().pop().unwrap();
         if let Some(mut ops) = entry.csr_op {

riscv/src/components/mem.rs

@@ -461,7 +461,7 @@ impl Component for RVMem {
         Ok(())
     }
 
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         let entry = self.history.borrow_mut().pop().unwrap();
         if let Some(d) = entry.data {
             self.memory.write(

riscv/src/components/reg_file.rs

@@ -471,7 +471,7 @@ impl Component for RegFile {
         Ok(())
     }
 
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         //println!("unclock");
         let regop = self.history.0.borrow_mut().pop().unwrap();
         let mut regstore = self.registers.borrow_mut();

src/common.rs

@@ -108,7 +108,7 @@ pub trait Component {
         Ok(())
     }
     /// update component internal state
-    fn un_clock(&self) {}
+    fn un_clock(&self, _simulator: &Simulator) {}
     /// reset component internal state to initial value
     fn reset(&self) {}
 

src/components/probe_edit.rs

@@ -59,7 +59,7 @@ impl Component for ProbeEdit {
     }
 
     // reverse simulation, notice does not touch simulator state, its just internal
-    fn un_clock(&self) {
+    fn un_clock(&self, _: &Simulator) {
         let mut edit_history = self.edit_history.write().unwrap();
         trace!("{} history {:?}", self.id, edit_history);
         let _next = edit_history.pop().unwrap(); // pop the next editable value

src/simulator.rs

@@ -148,8 +148,8 @@
             {
                 if ordered_components
                     .iter()
                     .find(|node| node.get_id_ports().0 == seq_node_inputs.id)
                     .is_some()
                 {
                     panic!("Component {} read data from {}. Sequential to sequential is not allowed, consider adding a pass trough component", seq_node.get_id_ports().0, seq_node_inputs.id)
                 }
@@ -197,7 +197,7 @@
         };
 
         trace!("sim_state {:?}", simulator.sim_state);
-        simulator.clock();
+        simulator.reset();
         Ok(simulator)
     }
 
@@ -473,8 +473,9 @@
                 _ => self.running_state = RunningState::Stopped,
             };
 
-            for component in self.ordered_components.clone() {
-                component.un_clock();
+            // reverse eval order before uncloak
+            for component in self.ordered_components.clone().into_iter().rev() {
+                component.un_clock(self);
             }
         }
     }