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feat(hir): lower additional SystemVerilog constructs#293

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hongjr03 merged 8 commits into
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feat/sv-construct-batch
Jun 27, 2026
Merged

feat(hir): lower additional SystemVerilog constructs#293
hongjr03 merged 8 commits into
masterfrom
feat/sv-construct-batch

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Summary

  • Treat SystemVerilog program definitions as module-shaped types for IDE navigation and hover.
  • Resolve package-scoped names and explicit package import items through IDE definition/hover/rename paths.
  • Lower clocking blocks, checker declarations/instances, and covergroups into HIR arenas, source maps, scopes, and IDE outline/hover/navigation snapshots.

Validation

  • cargo test -p hir
  • cargo test -p ide
  • cargo test
  • cargo clippy --workspace --all-targets -- -D warnings

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Docs preview: https://vide.pascal-lab.net/preview/pr-293/

@hongjr03 hongjr03 force-pushed the feat/sv-construct-batch branch from cfdbfe1 to c803e8c Compare June 27, 2026 08:10
@hongjr03 hongjr03 merged commit 7b422e4 into master Jun 27, 2026
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@hongjr03 hongjr03 deleted the feat/sv-construct-batch branch June 27, 2026 08:13
@hongjr03 hongjr03 linked an issue Jun 27, 2026 that may be closed by this pull request
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Rename misses package import usage even when scope visibility is public

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