MIPS-Pipelined-CPU

Five stage RISC pipeline CPU based on the MIPS instruction set architecture and implemented in Verilog. Independently designed from scratch for my Advanced Digital Systems Class. To simulate or synthesize the system a Verilog compatible IDE must be used. I used Xilinx ISE Design Suite with with ISim Simulator (http://www.xilinx.com/products/design-tools/ise-design-suite.html). Once installed, run the the provided testbench which instantiates an instance of the CPU and provides it with a clock and reset signal. When the systems runs it executes a number of instrucitons that test the system (which can be found in the Instruction Memory module). When simulating the system use the provided wave form configuration file in order view all the relevant registers and signals.