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Fix compiler and color map memory. #2

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Fix compiler and color map memory. #2

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307d6d9
Fixes a forthytwo.exe run error on systems where the comma is a decim…
pkuzmin Oct 31, 2020
970e357
The color map write clock port changed to cpuClk.
pkuzmin Oct 31, 2020
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Binary file modified bin/forthytwo.exe
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3 changes: 2 additions & 1 deletion forthytwoCompiler/src/util.cs
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Original file line number Diff line number Diff line change
@@ -1,5 +1,6 @@
using System;
using System.Collections.Generic;
using System.Globalization;

static class util {

Expand Down Expand Up @@ -45,7 +46,7 @@ public static bool tryParseNum(string text, out UInt32 val, bool enableFloat) {

if(enableFloat && text.Contains(".")) {
double vDouble;
if(Double.TryParse(text, out vDouble)) {
if(Double.TryParse(text, NumberStyles.Number, CultureInfo.CreateSpecificCulture("en-US"), out vDouble)) {
val = double2flm(vDouble);
return true;
}
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2 changes: 1 addition & 1 deletion fractalsProject/CMODA7_fractalDemo/CMODA7_fractalDemo.srcs/fpgatop.v
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Expand Up @@ -81,7 +81,7 @@ module fpgatop(CLK12, pioA, PMOD, uart_rxd_out, uart_txd_in, RGBLED, LED, BTN);
reg [31:0] io_din;

top #(.vgaX(vgaX), .vgaY(vgaY)) iTop
(.clk(clk200), .o_frameCount(frameCount),
(.clk(clk200), .cpuClk(cpuClk), .o_frameCount(frameCount),
.i_run(cpuReg[5][0]), .i_simFlush(cpuReg[5][1]),
.vgaClk(vgaClk), .o_RED(vgaRed), .o_GREEN(vgaGreen), .o_BLUE(vgaBlue), .o_HSYNC(vgaHsync), .o_VSYNC(vgaVsync),
.i_x0(cpuReg[0]), .i_y0(cpuReg[2]), .i_dxCol(cpuReg[1]), .i_dyCol(cpuReg[7]), .i_dxRow(cpuReg[6]), .i_dyRow(cpuReg[3]), .i_maxiter(cpuReg[4][7:0]),
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5 changes: 3 additions & 2 deletions fractalsProject/CMODA7_fractalDemo/CMODA7_fractalDemo.srcs/mandel.v
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Expand Up @@ -651,7 +651,7 @@ module generator(clk,
//assign o_res = EF_DEBUG_res;
endmodule

module top(clk, vgaClk, o_frameCount, i_run, i_simFlush,
module top(clk, vgaClk, cpuClk, o_frameCount, i_run, i_simFlush,
o_RED, o_GREEN, o_BLUE, o_HSYNC, o_VSYNC,
i_x0, i_y0, i_dxCol, i_dxRow, i_dyCol, i_dyRow, i_maxiter,
i_wrColMap, i_addrColMap, i_valColMap);
Expand All @@ -661,6 +661,7 @@ module top(clk, vgaClk, o_frameCount, i_run, i_simFlush,

input wire clk;
input wire vgaClk;
input wire cpuClk;

output wire [3:0] o_frameCount;
input wire i_run;
Expand Down Expand Up @@ -742,7 +743,7 @@ module top(clk, vgaClk, o_frameCount, i_run, i_simFlush,
// vga color mapping and blanking
// ================================================================================
reg [2:0] colMap[0:63];
always @(posedge clk)
always @(posedge cpuClk)
if (i_wrColMap)
colMap[i_addrColMap] <= i_valColMap;

Expand Down