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sobel-edge-detection-fpga
sobel-edge-detection-fpga PublicA convolution-based Sobel edge detection system on an A7-100T FPGA.
Verilog
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osmosis
osmosis PublicA digital hardware implementation of a cell membrane simulation game designed for an Artix-7 FPGA using Verilog.
Verilog
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gate-level-alu
gate-level-alu PublicA 4-bit Arithmetic Logic Unit (ALU) built at gate level abstraction and implemented on the Basys 3 Artix-7 FPGA.
Verilog
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