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A FPGA friendly 32 bit RISC-V CPU implementation
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minRISC/VexRiscv
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A FPGA friendly 32 bit RISC-V CPU implementation
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- Assembly 64.1%
- Scala 23.1%
- C++ 5.7%
- C 4.7%
- VHDL 1.0%
- Makefile 0.9%
- Other 0.5%