update rt1015 sdk to version 2.8.2

Author: hathach

sdk/devices/MIMXRT1015/MIMXRT1015.h

@@ -1,13 +1,13 @@
 /*
 ** ###################################################################
 **     Version:             rev. 1.1, 2019-02-20
-**     Build:               b190221
+**     Build:               b200211
 **
 **     Abstract:
 **         Chip specific module features.
 **
 **     Copyright 2016 Freescale Semiconductor, Inc.
-**     Copyright 2016-2019 NXP
+**     Copyright 2016-2020 NXP
 **     All rights reserved.
 **
 **     SPDX-License-Identifier: BSD-3-Clause
@@ -109,6 +109,8 @@
 #define FSL_FEATURE_SOC_USBNC_COUNT (1)
 /* @brief USBPHY availability on the SoC. */
 #define FSL_FEATURE_SOC_USBPHY_COUNT (1)
+/* @brief USB_ANALOG availability on the SoC. */
+#define FSL_FEATURE_SOC_USB_ANALOG_COUNT (1)
 /* @brief WDOG availability on the SoC. */
 #define FSL_FEATURE_SOC_WDOG_COUNT (2)
 /* @brief XBARA availability on the SoC. */
@@ -131,6 +133,8 @@
 
 /* @brief Has DMA model control(bit field CTRL[DMA_MODE_SEL]). */
 #define FSL_FEATURE_ADC_ETC_HAS_CTRL_DMA_MODE_SEL (1)
+/* @brief Has TRIGm_CHAIN_a_b IEn_EN. */
+#define FSL_FEATURE_ADC_ETC_HAS_TRIGm_CHAIN_a_b_IEn_EN (0)
 
 /* AOI module features */
 
@@ -139,6 +143,28 @@
 /* @brief Number of events related to number of registers AOIx_BFCRT01n/AOIx_BFCRT23n. */
 #define FSL_FEATURE_AOI_EVENT_COUNT (4)
 
+/* CCM module features */
+
+/* @brief Is affected by errata with ID 50235 (Incorrect clock setting for CAN affects by LPUART clock gate). */
+#define FSL_FEATURE_CCM_HAS_ERRATA_50235 (0)
+
+/* DCDC module features */
+
+/* @brief Has CTRL register (register CTRL0/1). */
+#define FSL_FEATURE_DCDC_HAS_CTRL_REG (0)
+/* @brief DCDC VDD output count. */
+#define FSL_FEATURE_DCDC_VDD_OUTPUT_COUNT (1)
+/* @brief Has no current alert function (register bit field REG0[CURRENT_ALERT_RESET]). */
+#define FSL_FEATURE_DCDC_HAS_NO_CURRENT_ALERT_FUNC (0)
+/* @brief Has switching converter differential mode (register bit field REG1[LOOPCTRL_EN_DF_HYST]). */
+#define FSL_FEATURE_DCDC_HAS_SWITCHING_CONVERTER_DIFFERENTIAL_MODE (0)
+/* @brief Has register bit field REG0[REG_DCDC_IN_DET]. */
+#define FSL_FEATURE_DCDC_HAS_REG0_DCDC_IN_DET (0)
+/* @brief Has no register bit field REG0[EN_LP_OVERLOAD_SNS]. */
+#define FSL_FEATURE_DCDC_HAS_NO_REG0_EN_LP_OVERLOAD_SNS (0)
+/* @brief Has register bit field REG3[REG_FBK_SEL]). */
+#define FSL_FEATURE_DCDC_HAS_REG3_FBK_SEL (0)
+
 /* EDMA module features */
 
 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */
@@ -207,13 +233,19 @@
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_BANK_SIZE (32768)
 /* @brief Total Bank numbers */
 #define FSL_FEATURE_FLEXRAM_INTERNAL_RAM_TOTAL_BANK_NUMBERS (4)
+/* @brief Has FLEXRAM_MAGIC_ADDR. */
+#define FSL_FEATURE_FLEXRAM_HAS_MAGIC_ADDR (0)
 
 /* FLEXSPI module features */
 
 /* @brief FlexSPI AHB buffer count */
 #define FSL_FEATURE_FLEXSPI_AHB_BUFFER_COUNTn(x) (4)
 /* @brief FlexSPI has no data learn. */
 #define FSL_FEATURE_FLEXSPI_HAS_NO_DATA_LEARN (1)
+/* @brief There is AHBBUSERROREN bit in INTEN register. */
+#define FSL_FEATURE_FLEXSPI_HAS_INTEN_AHBBUSERROREN (0)
+/* @brief There is CLRAHBTX_RXBUF bit in AHBCR register. */
+#define FSL_FEATURE_FLEXSPI_HAS_AHBCR_CLRAHBTX_RXBUF (0)
 
 /* GPC module features */
 
@@ -335,7 +367,12 @@
 
 /* OCOTP module features */
 
-/* No feature definitions */
+/* @brief Has timing control, (register TIMING). */
+#define FSL_FEATURE_OCOTP_HAS_TIMING_CTRL (1)
+/* @brief Support lock eFuse word write lock, (CTRL[WORDLOCK]). */
+#define FSL_FEATURE_OCOTP_HAS_WORDLOCK (0)
+/* @brief Has status register. (Register HW_OCOTP_OUT_STATUS0). */
+#define FSL_FEATURE_OCOTP_HAS_STATUS (0)
 
 /* PIT module features */
 
@@ -352,24 +389,12 @@
 
 /* PWM module features */
 
-/* @brief Number of each EflexPWM module channels (outputs). */
-#define FSL_FEATURE_PWM_CHANNEL_COUNT (12U)
-/* @brief Number of EflexPWM module A channels (outputs). */
-#define FSL_FEATURE_PWM_CHANNELA_COUNT (4U)
-/* @brief Number of EflexPWM module B channels (outputs). */
-#define FSL_FEATURE_PWM_CHANNELB_COUNT (4U)
-/* @brief Number of EflexPWM module X channels (outputs). */
-#define FSL_FEATURE_PWM_CHANNELX_COUNT (4U)
-/* @brief Number of each EflexPWM module compare channels interrupts. */
-#define FSL_FEATURE_PWM_CMP_INT_HANDLER_COUNT (4U)
-/* @brief Number of each EflexPWM module reload channels interrupts. */
-#define FSL_FEATURE_PWM_RELOAD_INT_HANDLER_COUNT (4U)
-/* @brief Number of each EflexPWM module capture channels interrupts. */
-#define FSL_FEATURE_PWM_CAP_INT_HANDLER_COUNT (1U)
-/* @brief Number of each EflexPWM module reload error channels interrupts. */
-#define FSL_FEATURE_PWM_RERR_INT_HANDLER_COUNT (1U)
-/* @brief Number of each EflexPWM module fault channels interrupts. */
-#define FSL_FEATURE_PWM_FAULT_INT_HANDLER_COUNT (1U)
+/* @brief If EflexPWM has module A channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELA (1)
+/* @brief If EflexPWM has module B channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELB (1)
+/* @brief If EflexPWM has module X channels (outputs). */
+#define FSL_FEATURE_PWM_HAS_CHANNELX (1)
 /* @brief Number of submodules in each EflexPWM module. */
 #define FSL_FEATURE_PWM_SUBMODULE_COUNT (4U)
 
@@ -413,6 +438,10 @@
 #define FSL_FEATURE_SAI_HAS_MDR (0)
 /* @brief Has support the BCLK bypass mode when BCLK = MCLK. */
 #define FSL_FEATURE_SAI_HAS_BCLK_BYPASS (0)
+/* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */
+#define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0)
+/* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */
+#define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (1)
 
 /* SNVS module features */
 
@@ -495,6 +524,13 @@
 /* @brief Number of endpoints supported */
 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8)
 
+/* USBPHY module features */
+
+/* @brief USBPHY contain DCD analog module */
+#define FSL_FEATURE_USBPHY_HAS_DCD_ANALOG (0)
+/* @brief USBPHY has register TRIM_OVERRIDE_EN */
+#define FSL_FEATURE_USBPHY_HAS_TRIM_OVERRIDE_EN (0)
+
 /* XBARA module features */
 
 /* @brief Number of interrupt requests. */

sdk/devices/MIMXRT1015/MIMXRT1015.xml

@@ -65,7 +65,7 @@ extern ARM_DRIVER_I2C Driver_I2C6;
 
 /* I2C Driver state flags */
 #define I2C_FLAG_UNINIT (0)
-#define I2C_FLAG_INIT (1 << 0)
-#define I2C_FLAG_POWER (1 << 1)
+#define I2C_FLAG_INIT   (1 << 0)
+#define I2C_FLAG_POWER  (1 << 1)
 
 #endif /* _FSL_LPI2C_CMSIS_H_ */

sdk/devices/MIMXRT1015/MIMXRT1015_features.h

@@ -28,7 +28,7 @@
 #if ((RTE_SPI0 && defined(LPSPI0)) || (RTE_SPI1 && defined(LPSPI1)) || (RTE_SPI2 && defined(LPSPI2)) || \
      (RTE_SPI3 && defined(LPSPI3)) || (RTE_SPI4 && defined(LPSPI4)) || (RTE_SPI5 && defined(LPSPI5)))
 
-#define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 1) /* driver version */
+#define ARM_LPSPI_DRV_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2, 2) /* driver version */
 
 /*
  * ARMCC does not support split the data section automatically, so the driver
@@ -572,10 +572,11 @@ static int32_t LPSPI_EdmaSend(const void *data, uint32_t num, cmsis_lpspi_edma_d
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.rxData   = NULL;
     xfer.txData   = (uint8_t *)data;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -612,10 +613,11 @@ static int32_t LPSPI_EdmaReceive(void *data, uint32_t num, cmsis_lpspi_edma_driv
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.txData   = NULL;
     xfer.rxData   = (uint8_t *)data;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -655,10 +657,11 @@ static int32_t LPSPI_EdmaTransfer(const void *data_out,
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.txData   = (uint8_t *)data_out;
     xfer.rxData   = (uint8_t *)data_in;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -693,6 +696,7 @@ static uint32_t LPSPI_EdmaGetCount(cmsis_lpspi_edma_driver_state_t *lpspi)
 {
     uint32_t cnt;
     size_t bytes;
+    uint32_t datawidth = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     if (LPSPI_IsMaster(lpspi->resource->base))
     {
@@ -706,6 +710,7 @@ static uint32_t LPSPI_EdmaGetCount(cmsis_lpspi_edma_driver_state_t *lpspi)
                 EDMA_GetRemainingMajorLoopCount(lpspi->dmaResource->rxEdmaBase, lpspi->dmaResource->rxEdmaChannel);
         cnt = lpspi->handle->slaveHandle.totalByteCount - bytes;
     }
+    cnt /= ((datawidth + 8U) / 8U);
     return cnt;
 }
 
@@ -943,10 +948,11 @@ static int32_t LPSPI_InterruptSend(const void *data, uint32_t num, cmsis_lpspi_i
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.rxData   = NULL;
     xfer.txData   = (uint8_t *)data;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -983,10 +989,11 @@ static int32_t LPSPI_InterruptReceive(void *data, uint32_t num, cmsis_lpspi_inte
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.txData   = NULL;
     xfer.rxData   = (uint8_t *)data;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -1026,10 +1033,11 @@ static int32_t LPSPI_InterruptTransfer(const void *data_out,
     int32_t ret;
     status_t status;
     lpspi_transfer_t xfer = {0};
+    uint32_t datawidth    = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
 
     xfer.txData   = (uint8_t *)data_out;
     xfer.rxData   = (uint8_t *)data_in;
-    xfer.dataSize = num;
+    xfer.dataSize = num * ((datawidth + 8U) / 8U);
 
     LPSPI_SetTransferConfigFlags(LPSPI_IsMaster(lpspi->resource->base), lpspi->resource->instance, &xfer);
 
@@ -1062,14 +1070,19 @@ static int32_t LPSPI_InterruptTransfer(const void *data_out,
 }
 static uint32_t LPSPI_InterruptGetCount(cmsis_lpspi_interrupt_driver_state_t *lpspi)
 {
+    uint32_t cnt;
+    uint32_t datawidth = (lpspi->resource->base->TCR & LPSPI_TCR_FRAMESZ_MASK) >> LPSPI_TCR_FRAMESZ_SHIFT;
     if (LPSPI_IsMaster(lpspi->resource->base))
     {
-        return lpspi->handle->masterHandle.totalByteCount - lpspi->handle->masterHandle.rxRemainingByteCount;
+        cnt = lpspi->handle->masterHandle.totalByteCount - lpspi->handle->masterHandle.rxRemainingByteCount;
     }
     else
     {
-        return lpspi->handle->slaveHandle.totalByteCount - lpspi->handle->slaveHandle.rxRemainingByteCount;
+        cnt = lpspi->handle->slaveHandle.totalByteCount - lpspi->handle->slaveHandle.rxRemainingByteCount;
     }
+    cnt /= ((datawidth + 8U) / 8U);
+
+    return cnt;
 }
 
 static int32_t LPSPI_InterruptControl(uint32_t control, uint32_t arg, cmsis_lpspi_interrupt_driver_state_t *lpspi)

sdk/devices/MIMXRT1015/arm/MIMXRT1015_QuadSPI_4KB_SEC.FLM

@@ -57,9 +57,9 @@ extern ARM_DRIVER_SPI Driver_SPI5;
 #endif /* LPSPI5 */
 
 /* SPI Driver state flags */
-#define SPI_FLAG_UNINIT (0)
-#define SPI_FLAG_INIT (1 << 0)
-#define SPI_FLAG_POWER (1 << 1)
+#define SPI_FLAG_UNINIT     (0)
+#define SPI_FLAG_INIT       (1 << 0)
+#define SPI_FLAG_POWER      (1 << 1)
 #define SPI_FLAG_CONFIGURED (1 << 2)
 
 #endif

sdk/devices/MIMXRT1015/cmsis_drivers/fsl_lpi2c_cmsis.h

@@ -81,9 +81,9 @@ extern ARM_DRIVER_USART Driver_USART5;
 #endif
 
 /* USART Driver state flags */
-#define USART_FLAG_UNINIT (0)
-#define USART_FLAG_INIT (1 << 0)
-#define USART_FLAG_POWER (1 << 1)
+#define USART_FLAG_UNINIT     (0)
+#define USART_FLAG_INIT       (1 << 0)
+#define USART_FLAG_POWER      (1 << 1)
 #define USART_FLAG_CONFIGURED (1 << 2)
 
 #endif /* _FSL_LPUART_CMSIS_H_ */

sdk/devices/MIMXRT1015/cmsis_drivers/fsl_lpspi_cmsis.c

@@ -1,6 +1,6 @@
 /*
  * Copyright (c) 2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
+ * Copyright 2016-2019 NXP
  * All rights reserved.
  *
  * SPDX-License-Identifier: BSD-3-Clause
@@ -144,7 +144,7 @@ void ADC_GetDefaultConfig(adc_config_t *config)
     assert(NULL != config);
 
     /* Initializes the configure structure to zero. */
-    memset(config, 0, sizeof(*config));
+    (void)memset(config, 0, sizeof(*config));
 
     config->enableAsynchronousClockOutput = true;
     config->enableOverWrite               = false;
@@ -244,7 +244,7 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
     while (0U != (base->GC & ADC_GC_CAL_MASK))
     {
         /* Check the CALF when the calibration is active. */
-        if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag))
+        if (0U != (ADC_GetStatusFlags(base) & (uint32_t)kADC_CalibrationFailedFlag))
         {
             status = kStatus_Fail;
             break;
@@ -256,13 +256,13 @@ status_t ADC_DoAutoCalibration(ADC_Type *base)
     {
         status = kStatus_Fail;
     }
-    if (0U != (ADC_GetStatusFlags(base) & kADC_CalibrationFailedFlag)) /* Check the CALF status. */
+    if (0U != (ADC_GetStatusFlags(base) & (uint32_t)kADC_CalibrationFailedFlag)) /* Check the CALF status. */
     {
         status = kStatus_Fail;
     }
 
     /* Clear conversion done flag. */
-    ADC_GetChannelConversionValue(base, 0U);
+    (void)ADC_GetChannelConversionValue(base, 0U);
 
 #if !(defined(FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE) && FSL_FEATURE_ADC_SUPPORT_HARDWARE_TRIGGER_REMOVE)
     /* Restore original trigger mode. */
@@ -336,6 +336,7 @@ void ADC_SetHardwareCompareConfig(ADC_Type *base, const adc_hardware_compare_con
             tmp32 |= ADC_GC_ACFGT_MASK | ADC_GC_ACREN_MASK;
             break;
         default:
+            assert(false);
             break;
     }
     base->GC = tmp32;
@@ -382,11 +383,11 @@ void ADC_ClearStatusFlags(ADC_Type *base, uint32_t mask)
 {
     uint32_t tmp32 = 0;
 
-    if (0U != (mask & kADC_CalibrationFailedFlag))
+    if (0U != (mask & (uint32_t)kADC_CalibrationFailedFlag))
     {
         tmp32 |= ADC_GS_CALF_MASK;
     }
-    if (0U != (mask & kADC_ConversionActiveFlag))
+    if (0U != (mask & (uint32_t)kADC_ConversionActiveFlag))
     {
         tmp32 |= ADC_GS_ADACT_MASK;
     }