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AetherTrade: Hybrid High-Frequency Trading (HFT) Platform

Latency Hardware Workflow License

AetherTrade is an ultra-low-latency hybrid HFT platform targeting Xilinx UltraScale+ FPGAs. It implements line-rate NASDAQ ITCH 5.0 parsing, URAM-based order books, and pre-trade risk checks with a high-performance C++ control path.

🏗️ System Architecture

The system is architected following the AMD UltraFast Design Methodology, ensuring deterministic performance and high-frequency operation.

Hardware (FPGA "Fast Path")

  • 10GbE MAC/PHY: Direct wire-level market data ingestion.
  • NASDAQ ITCH 5.0 Parser: Line-rate binary protocol parsing in Verilog.
  • URAM Order Book: Single-cycle access to L2 market depth using UltraRAM.
  • HLS Risk Engine: Pre-trade risk validation (Price-Band, Wash-Trade) implemented in C++ (HLS) for < 50ns latency.

Software (Host "Control Path")

  • PCIe DMA: Zero-copy data transfer between hardware and host using XDMA/QDMA.
  • Strategy Engine: High-performance C++ engine with CPU core isolation and thread pinning.
  • Telemetry Bridge: ZeroMQ-based broadcasting of live PnL and alpha signals.
  • Dashboard: Premium glassmorphism UI for real-time operational monitoring.

📂 Project Structure

.
├── hdl/                    # Verilog/SystemVerilog RTL (Parser, Order Book)
├── hls/                    # C++ High-Level Synthesis (Risk Engine)
├── src/                    # Host C++ Strategy Engine and DMA logic
├── ui/                     # Monitoring Dashboard (HTML/CSS/JS)
├── tests/                  # Hardware/Software test suites
├── scripts/                # Python verification tools (PCAP Replay)
├── specs/                  # SDD Design Artifacts (Spec Kit)
├── .specify/               # Spec Kit internal infrastructure
└── .gemini/                # Agent-specific skills and commands

🚀 Getting Started

Prerequisites

  • Hardware: Xilinx UltraScale+ FPGA.
  • Tooling: Vivado/Vitis 2023.2+, GCC/Clang, Python 3.10+.
  • Package Manager: uv (for verification scripts).

Installation & Setup

  1. Initialize Environment:
    uv sync
  2. Build Hardware: Open Vivado and source the TCL scripts (TBD) to generate the bitstream.
  3. Build Software:
    clang++ -O3 -I src src/strategy_engine.cpp -o strategy_engine -lzmq

🧪 Verification & TDD Workflow

This project follows Spec-Driven Development (SDD). The Python files in scripts/ are used for hardware verification only and are not synthesized into the FPGA logic.

Market Data Simulation

To verify the hardware parser logic without a physical feed:

uv run python scripts/verify_pcap.py data/sample_itch.pcap

🛠️ Spec Kit Integration

This repository is powered by GitHub Spec Kit for the Gemini CLI. Use the following slash commands to drive development:

  • /speckit.specify - Create functional requirements.
  • /speckit.plan - Generate technical implementation plans.
  • /speckit.tasks - Break plans into actionable task lists.
  • /speckit.implement - Execute implementation following TDD.

⚖️ License

This project is licensed under the MIT License - see the LICENSE file for details.

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Ultra-low-latency hybrid HFT platform targeting Xilinx UltraScale+ FPGAs. Implements line-rate NASDAQ ITCH 5.0 parsing, URAM-based order books, and pre-trade risk checks with a high-performance C++ control path.

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