fased-verilog

Verilog code for the IEEE CAL paper "Fusing adds and shifts for efficient dot products" (http://doi.org/10.1109/LCA.2025.3637718) including baselines and Fased MAC (Multiply-Accumulate) designs, along with scripts for simulation and synthesis.

Results from the paper were obtained with the following software versions:

• ubuntu 22.04
• siliconcompiler 0.26.2
• Yosys 0.43 (git sha1 ead4718e5, g++ 11.4.0-1ubuntu1~22.04 -fPIC -Os)
• OpenRoad OpenROAD v2.0-17598-ga008522d8
• Python 3.12
• ModelSim - Intel FPGA Starter Edition 2020.1
• ASAP7 PDK

Repository is organized in 3 directories:

1. verilog - contains the Verilog source files for the designs
2. simulation - contains scripts for simulation

Simulation

Launch simulation using the script run_sim.sh in the simulation directory. Simulation is performed through command line using ModelSim. At the minimum, it requires the following parameters:

• --design - the design name, can be one of [base_afw, base_avw, base_bfw, base_bvw, fased_fw, fased_vw]
• --a_bits - the activation width in bits, only 8 is supported currently
• --w_bits - the weight width in bits, can be 2, 4, or 8

Simulation scripts verify results for all possible values. After simulation, the script will compare the results with the ground truth and print the result.