This project is a web-based tool for visualizing the fetch-decode-execute cycle of a simple RISC-V CPU. It helps students and educators understand how binary instructions are fetched from memory, decoded into fields, and executed step-by-step.
- Visualizes instruction memory with binary and assembly
- Color-coded breakdown of instruction fields (opcode, registers, immediates)
- Step through each CPU cycle: Fetch, Decode, Execute
- See register state updates and branch behavior
- Clean, interactive UI for learning and teaching
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Install uv:
pip install uv
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Run the simulator:
uv run main.py
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Open your browser:
- Go to http://localhost:5000
- Enter your RISC-V assembly program in the editor.
- Click Simulate to visualize the instruction cycle.
- Step through each phase (Fetch, Decode, Execute) and see how instructions are processed.
- Click Edit Program to modify your code and re-run the simulation.