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README 
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CACTI-ECC: Extended Cache Modeling with ECC Logic Overheads

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1. Overview
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This repository provides an enhanced version of the CACTI cache modeling framework with support for comprehensive Error Correcting Code (ECC) modeling, including both:

a. Memory-induced overheads (M-overheads) — already supported in baseline CACTI
b. Memory and Logic-induced overheads (ML-overheads) — newly added in this work

- Traditional CACTI assumes ECC logic delay and energy are negligible. This extension removes that assumption and enables accurate modeling of ECC encode/decode logic, which is critical for modern safety-critical SoCs.
- Full ECC Overhead Modeling (M + L)
	Models ECC storage overheads (extra check bits)
	Adds combinational logic delay and energy
	Captures critical path impact of ECC logic

Ignoring ECC logic overheads leads to underestimated latency, underestimated energy and misleading architectural decisions
This extension enables:
	Accurate performance evaluation
	Realistic energy estimation

This framework allows architects to explore:
	Performance vs reliability trade-offs
	Cache hierarchy ECC placement
	Energy-aware ECC design
	Technology scaling effects

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2. Error Correction Modes supported
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- Support for ECC Modes
  High Reliability (HR) Mode: In-line ECC (correction before use), maximum reliability, higher latency and energy
  High Performance (HP) Mode: Parallel ECC (correction after access), lower latency, possible re-access on error
	HRSA (High Reliability Serial Access)
	HRPA (High Reliability Parallel Access)
	HPSA (High Performance Serial Access)
	HPPA (High Performance Parallel Access)

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3. Modeling Validation
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- The model has been validated using gem5 on:
	SPEC CPU 2006 workloads
	MiBench workloads
	In-order and out-of-order cores
	Iso-frequency and hetero-frequency setups

- Technology nodes:
	22nm
	32nm
	40nm
	90nm

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4. Additional flags in cache.cfg
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To support ECC modeling, following configuration options are supported in cache.cfg which can be provided through the command line arguments in the usual cacti run command post compiling.
Note: To enable, ECC modeling, the existing option "-Add ECC" must be set to "true".

a. ECC code: Supported codes: Hamming, Hsiao
  -ECC code "Hamming"
  -ECC code "Hsiao"

b. ECC mode: Supported options: HR (High Reliability), HP (High Performance) 
  -ECC mode "HP"
  -ECC mode "HR"

c. ECC level: Supported options: ML (Memory+Logic), M (Memory)
  -ECC level: "ML"
  -ECC level: "M"


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5. Configuring different Error Correction Modes
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Using these switches, along with "-access mode" enables, the different Error Correction Modes are configured.
Along with these, adjust the switches '-ECC level' and '-ECC code' appropriately as needed.
a. HRSA 
	-access mode (normal, sequential, fast) - "sequential"
	-ECC mode "HR"
b. HRPA
	-access mode (normal, sequential, fast) - "normal"
	-ECC mode "HR"
c. HPSA 
	-access mode (normal, sequential, fast) - "sequential"
	-ECC mode "HP"
d. HPPA
	-access mode (normal, sequential, fast) - "normal"
	-ECC mode "HP"


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6. Citing us
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This repository is based on following work. Users are advised to refer to the article for details.
'Modeling Energy and Delay for ECC-Enabled Cache Architectures', IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2026.3665117
The article can be referred within this repository at: article_pdf/Modeling_Energy_and_Delay_for_ECC-Enabled_Cache_Architectures.pdf

We expect this repository to be useful for researchers and architects.
If you find this tool useful, you can cite us using:

Plaintext:
  D. Joshi et al., "Modeling Energy and Delay for ECC-Enabled Cache Architectures," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2026.3665117. keywords: {Error correction codes;Logic;Delays;Arrays;Logic arrays;Mathematical models;Logic gates;Error correction;System-on-chip;Reliability engineering}

BibTeX:
  @ARTICLE{11396938,
  author={Joshi, Dinesh and Bagchi, Aritra and Agarwal, Ayushi and Modi, Garima and Srivastava, Neha and Roy, Sourav and Panda, Preeti Ranjan},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems}, 
  title={Modeling Energy and Delay for ECC-Enabled Cache Architectures}, 
  year={2026},
  volume={},
  number={},
  pages={1-1},
  keywords={Error correction codes;Logic;Delays;Arrays;Logic arrays;Mathematical models;Logic gates;Error correction;System-on-chip;Reliability engineering},
  doi={10.1109/TCAD.2026.3665117}}

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Contributions and suggestions are welcome!
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