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[ibex] Add Zcb and Zcmp extensions #28997

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[ibex] Add Zcb and Zcmp extensions #28997

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8607531
Update lowrisc_ibex to lowRISC/ibex@246849ed
SamuelRiedel Dec 19, 2025
9377420
Update lowrisc_ibex to lowRISC/ibex@0c233f54
SamuelRiedel Dec 23, 2025
f3411ef
[top,rv_core_ibex] Add the Zc* parameter to topgen
SamuelRiedel Dec 23, 2025
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8 changes: 8 additions & 0 deletions hw/ip_templates/rv_core_ibex/data/rv_core_ibex.hjson.tpl
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Expand Up @@ -367,6 +367,14 @@
expose: "true"
},

{ name: "RV32ZC"
type: "ibex_pkg::rv32zc_e"
default: "ibex_pkg::RV32ZcaZcbZcmp"
desc: "RV32ZC"
local: "false"
expose: "true"
},

{ name: "RegFile"
type: "ibex_pkg::regfile_e"
default: "ibex_pkg::RegFileFF"
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2 changes: 2 additions & 0 deletions hw/ip_templates/rv_core_ibex/rtl/rv_core_ibex.sv.tpl
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Expand Up @@ -28,6 +28,7 @@ module ${module_instance_name}
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF,
parameter bit BranchTargetALU = 1'b1,
parameter bit WritebackStage = 1'b1,
Expand Down Expand Up @@ -418,6 +419,7 @@ module ${module_instance_name}
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.WritebackStage ( WritebackStage ),
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10 changes: 10 additions & 0 deletions hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
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Expand Up @@ -10179,6 +10179,7 @@
RV32E: "0"
RV32M: ibex_pkg::RV32MSingleCycle
RV32B: ibex_pkg::RV32BOTEarlGrey
RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
RegFile: ibex_pkg::RegFileFF
BranchTargetALU: "1"
WritebackStage: "1"
Expand Down Expand Up @@ -10366,6 +10367,15 @@
expose: "true"
name_top: RvCoreIbexRV32B
}
{
name: RV32ZC
desc: RV32ZC
type: ibex_pkg::rv32zc_e
default: ibex_pkg::RV32ZcaZcbZcmp
local: "false"
expose: "true"
name_top: RvCoreIbexRV32ZC
}
{
name: RegFile
desc: Reg file
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1 change: 1 addition & 0 deletions hw/top_darjeeling/data/top_darjeeling.hjson
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Expand Up @@ -1088,6 +1088,7 @@
RV32E: "0",
RV32M: "ibex_pkg::RV32MSingleCycle",
RV32B: "ibex_pkg::RV32BOTEarlGrey",
RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
RegFile: "ibex_pkg::RegFileFF",
BranchTargetALU: "1",
WritebackStage: "1",
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8 changes: 8 additions & 0 deletions hw/top_darjeeling/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
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Expand Up @@ -341,6 +341,14 @@
expose: "true"
},

{ name: "RV32ZC"
type: "ibex_pkg::rv32zc_e"
default: "ibex_pkg::RV32ZcaZcbZcmp"
desc: "RV32ZC"
local: "false"
expose: "true"
},

{ name: "RegFile"
type: "ibex_pkg::regfile_e"
default: "ibex_pkg::RegFileFF"
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2 changes: 2 additions & 0 deletions hw/top_darjeeling/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
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Expand Up @@ -28,6 +28,7 @@ module rv_core_ibex
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF,
parameter bit BranchTargetALU = 1'b1,
parameter bit WritebackStage = 1'b1,
Expand Down Expand Up @@ -405,6 +406,7 @@ module rv_core_ibex
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.WritebackStage ( WritebackStage ),
Expand Down
2 changes: 2 additions & 0 deletions hw/top_darjeeling/rtl/autogen/top_darjeeling.sv
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Expand Up @@ -143,6 +143,7 @@ module top_darjeeling #(
parameter bit RvCoreIbexRV32E = 0,
parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
parameter bit RvCoreIbexBranchTargetALU = 1,
parameter bit RvCoreIbexWritebackStage = 1,
Expand Down Expand Up @@ -2729,6 +2730,7 @@ module top_darjeeling #(
.RV32E(RvCoreIbexRV32E),
.RV32M(RvCoreIbexRV32M),
.RV32B(RvCoreIbexRV32B),
.RV32ZC(RvCoreIbexRV32ZC),
.RegFile(RvCoreIbexRegFile),
.BranchTargetALU(RvCoreIbexBranchTargetALU),
.WritebackStage(RvCoreIbexWritebackStage),
Expand Down
10 changes: 10 additions & 0 deletions hw/top_earlgrey/data/autogen/top_earlgrey.gen.hjson
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Expand Up @@ -9110,6 +9110,7 @@
RV32E: "0"
RV32M: ibex_pkg::RV32MSingleCycle
RV32B: ibex_pkg::RV32BOTEarlGrey
RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
RegFile: ibex_pkg::RegFileFF
BranchTargetALU: "1"
WritebackStage: "1"
Expand Down Expand Up @@ -9296,6 +9297,15 @@
expose: "true"
name_top: RvCoreIbexRV32B
}
{
name: RV32ZC
desc: RV32ZC
type: ibex_pkg::rv32zc_e
default: ibex_pkg::RV32ZcaZcbZcmp
local: "false"
expose: "true"
name_top: RvCoreIbexRV32ZC
}
{
name: RegFile
desc: Reg file
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1 change: 1 addition & 0 deletions hw/top_earlgrey/data/top_earlgrey.hjson
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Expand Up @@ -1028,6 +1028,7 @@
RV32E: "0",
RV32M: "ibex_pkg::RV32MSingleCycle",
RV32B: "ibex_pkg::RV32BOTEarlGrey",
RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
RegFile: "ibex_pkg::RegFileFF",
BranchTargetALU: "1",
WritebackStage: "1",
Expand Down
8 changes: 8 additions & 0 deletions hw/top_earlgrey/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
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Expand Up @@ -341,6 +341,14 @@
expose: "true"
},

{ name: "RV32ZC"
type: "ibex_pkg::rv32zc_e"
default: "ibex_pkg::RV32ZcaZcbZcmp"
desc: "RV32ZC"
local: "false"
expose: "true"
},

{ name: "RegFile"
type: "ibex_pkg::regfile_e"
default: "ibex_pkg::RegFileFF"
Expand Down
2 changes: 2 additions & 0 deletions hw/top_earlgrey/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
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Expand Up @@ -28,6 +28,7 @@ module rv_core_ibex
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF,
parameter bit BranchTargetALU = 1'b1,
parameter bit WritebackStage = 1'b1,
Expand Down Expand Up @@ -405,6 +406,7 @@ module rv_core_ibex
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.WritebackStage ( WritebackStage ),
Expand Down
2 changes: 2 additions & 0 deletions hw/top_earlgrey/rtl/autogen/top_earlgrey.sv
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Expand Up @@ -129,6 +129,7 @@ module top_earlgrey #(
parameter bit RvCoreIbexRV32E = 0,
parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
parameter bit RvCoreIbexBranchTargetALU = 1,
parameter bit RvCoreIbexWritebackStage = 1,
Expand Down Expand Up @@ -2828,6 +2829,7 @@ module top_earlgrey #(
.RV32E(RvCoreIbexRV32E),
.RV32M(RvCoreIbexRV32M),
.RV32B(RvCoreIbexRV32B),
.RV32ZC(RvCoreIbexRV32ZC),
.RegFile(RvCoreIbexRegFile),
.BranchTargetALU(RvCoreIbexBranchTargetALU),
.WritebackStage(RvCoreIbexWritebackStage),
Expand Down
10 changes: 10 additions & 0 deletions hw/top_englishbreakfast/data/autogen/top_englishbreakfast.gen.hjson
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Expand Up @@ -4133,6 +4133,7 @@
RV32E: "0"
RV32M: ibex_pkg::RV32MSingleCycle
RV32B: ibex_pkg::RV32BNone
RV32ZC: ibex_pkg::RV32ZcaZcbZcmp
RegFile: ibex_pkg::RegFileFF
BranchTargetALU: "1"
WritebackStage: "1"
Expand Down Expand Up @@ -4306,6 +4307,15 @@
expose: "true"
name_top: RvCoreIbexRV32B
}
{
name: RV32ZC
desc: RV32ZC
type: ibex_pkg::rv32zc_e
default: ibex_pkg::RV32ZcaZcbZcmp
local: "false"
expose: "true"
name_top: RvCoreIbexRV32ZC
}
{
name: RegFile
desc: Reg file
Expand Down
1 change: 1 addition & 0 deletions hw/top_englishbreakfast/data/top_englishbreakfast.hjson
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Expand Up @@ -604,6 +604,7 @@
RV32E: "0",
RV32M: "ibex_pkg::RV32MSingleCycle",
RV32B: "ibex_pkg::RV32BNone",
RV32ZC: "ibex_pkg::RV32ZcaZcbZcmp",
RegFile: "ibex_pkg::RegFileFF",
BranchTargetALU: "1",
WritebackStage: "1",
Expand Down
8 changes: 8 additions & 0 deletions hw/top_englishbreakfast/ip_autogen/rv_core_ibex/data/rv_core_ibex.hjson
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Expand Up @@ -341,6 +341,14 @@
expose: "true"
},

{ name: "RV32ZC"
type: "ibex_pkg::rv32zc_e"
default: "ibex_pkg::RV32ZcaZcbZcmp"
desc: "RV32ZC"
local: "false"
expose: "true"
},

{ name: "RegFile"
type: "ibex_pkg::regfile_e"
default: "ibex_pkg::RegFileFF"
Expand Down
2 changes: 2 additions & 0 deletions hw/top_englishbreakfast/ip_autogen/rv_core_ibex/rtl/rv_core_ibex.sv
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Expand Up @@ -28,6 +28,7 @@ module rv_core_ibex
parameter bit RV32E = 0,
parameter ibex_pkg::rv32m_e RV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RV32B = ibex_pkg::RV32BOTEarlGrey,
parameter ibex_pkg::rv32zc_e RV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RegFile = ibex_pkg::RegFileFF,
parameter bit BranchTargetALU = 1'b1,
parameter bit WritebackStage = 1'b1,
Expand Down Expand Up @@ -405,6 +406,7 @@ module rv_core_ibex
.RV32E ( RV32E ),
.RV32M ( RV32M ),
.RV32B ( RV32B ),
.RV32ZC ( RV32ZC ),
.RegFile ( RegFile ),
.BranchTargetALU ( BranchTargetALU ),
.WritebackStage ( WritebackStage ),
Expand Down
2 changes: 2 additions & 0 deletions hw/top_englishbreakfast/rtl/autogen/top_englishbreakfast.sv
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Expand Up @@ -65,6 +65,7 @@ module top_englishbreakfast #(
parameter bit RvCoreIbexRV32E = 0,
parameter ibex_pkg::rv32m_e RvCoreIbexRV32M = ibex_pkg::RV32MSingleCycle,
parameter ibex_pkg::rv32b_e RvCoreIbexRV32B = ibex_pkg::RV32BNone,
parameter ibex_pkg::rv32zc_e RvCoreIbexRV32ZC = ibex_pkg::RV32ZcaZcbZcmp,
parameter ibex_pkg::regfile_e RvCoreIbexRegFile = ibex_pkg::RegFileFF,
parameter bit RvCoreIbexBranchTargetALU = 1,
parameter bit RvCoreIbexWritebackStage = 1,
Expand Down Expand Up @@ -1296,6 +1297,7 @@ module top_englishbreakfast #(
.RV32E(RvCoreIbexRV32E),
.RV32M(RvCoreIbexRV32M),
.RV32B(RvCoreIbexRV32B),
.RV32ZC(RvCoreIbexRV32ZC),
.RegFile(RvCoreIbexRegFile),
.BranchTargetALU(RvCoreIbexBranchTargetALU),
.WritebackStage(RvCoreIbexWritebackStage),
Expand Down
2 changes: 1 addition & 1 deletion hw/vendor/lowrisc_ibex.lock.hjson
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Expand Up @@ -9,6 +9,6 @@
upstream:
{
url: https://github.com/lowRISC/ibex.git
rev: 0d1b1723253cdf804aad263e805544d54aa5aa57
rev: 0c233f54361d769f370889223acc456f2ac19d46
}
}
8 changes: 8 additions & 0 deletions hw/vendor/lowrisc_ibex/doc/01_overview/compliance.rst
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Expand Up @@ -47,6 +47,14 @@ In addition, the following instruction set extensions are available.
- 2.0
- always enabled

* - **Zcb**: Simple Code-Size Saving Instructions
- 1.0.0
- optional

* - **Zcmp**: Push/Pop/Move Code-Size Saving Instructions
- 1.0.0
- optional

* - **Smepmp** - PMP Enhancements for memory access and execution prevention on Machine mode
- 1.0
- always enabled in configurations with PMP see :ref:`PMP Enhancements<pmp-enhancements>`
Expand Down
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