Add Zcb and Zcmp extension RTL

[SamuelRiedel]

This PR adds only the RTL part of #2324. We will merge the DV alongside the compiler update once we also upstreamed the riscv-dv changes.

This PR adds support for the Zcb and Zcmp code-saving extensions. This support is implemented in a parameterizable way via the RV32ZC parameter, which allows choosing none, either, or both extensions. By default, both extensions are enabled because their combined hardware overhead is small, approximately 800 gate equivalents.

The Zcb extension introduces new compressed encodings for common instructions already supported in Ibex. The Zcmp extension introduces single compressed instructions that expand into multiple existing instructions within Ibex. For example, a stack push expands into multiple store instructions and a stack pointer update. Therefore, both extensions are implemented in the IF stage.

[andreaskurth]

LGTM, thanks @SamuelRiedel!

(For reference, see #2324 for DV and more detailed review comments.)

[marnovandermaas]

Very cool pull request this. Thanks for all your hard work. I just had a few small comments based on a code review.

[SamuelRiedel]

Thank you, @marnovandermaas. I implemented your feedback and ran the tests again. I will wait with the squashing until the end to make reviewing easier, since many of those commits are small bug fixes on top of Andreas's commit.

[SamuelRiedel]

The full test suite results with the new DV for this RTL can be found here: #2324 (comment)

The full regression results of this PR with the current DV is the following.

Note that the riscv_illegal_instr_test can currently fail if Zcb or Zcmp is enabled in the RTL but not yet supported in the DV. The updated DV handles these instructions correctly and passes all tests (#2324 (comment)). Disabling the Zcb and Zcmp extensions via the RV32ZC parameter also resolves the issue in the current version since Ibex will treat those instructions as illegal like the DV. Therefore, this behavior is currently expected.

Ibex Regression Results

Test Name	Passing	Total	Pass Rate
riscv_arithmetic_basic_test	10	10	100.0%
riscv_machine_mode_rand_test	10	10	100.0%
riscv_rand_instr_test	10	10	100.0%
riscv_rand_jump_test	9	10	90.0%
riscv_jump_stress_test	10	10	100.0%
riscv_loop_test	10	10	100.0%
riscv_mmu_stress_test	10	10	100.0%
riscv_illegal_instr_test	3	15	20.0%
riscv_hint_instr_test	10	10	100.0%
riscv_ebreak_test	10	10	100.0%
riscv_debug_basic_test	8	10	80.0%
riscv_debug_stress_test	15	15	100.0%
riscv_debug_branch_jump_test	10	10	100.0%
riscv_debug_instr_test	24	25	96.0%
riscv_debug_wfi_test	9	10	90.0%
riscv_dret_test	5	5	100.0%
riscv_debug_ebreak_test	15	15	100.0%
riscv_debug_ebreakmu_test	14	15	93.3%
riscv_debug_csr_entry_test	10	10	100.0%
riscv_irq_in_debug_mode_test	9	10	90.0%
riscv_debug_in_irq_test	10	10	100.0%
riscv_assorted_traps_interrupts_debug_test	4	10	40.0%
riscv_single_interrupt_test	15	15	100.0%
riscv_multiple_interrupt_test	10	10	100.0%
riscv_nested_interrupt_test	10	10	100.0%
riscv_interrupt_instr_test	25	25	100.0%
riscv_interrupt_wfi_test	15	15	100.0%
riscv_interrupt_csr_test	10	10	100.0%
riscv_csr_test	5	5	100.0%
riscv_unaligned_load_store_test	5	5	100.0%
riscv_mem_error_test	15	15	100.0%
riscv_mem_intg_error_test	42	50	84.0%
riscv_debug_single_step_test	12	15	80.0%
riscv_reset_test	15	15	100.0%
riscv_pc_intg_test	14	15	93.3%
riscv_rf_intg_test	100	100	100.0%
riscv_rf_ctrl_intg_test	15	15	100.0%
riscv_ram_intg_test	14	15	93.3%
riscv_icache_intg_test	15	15	100.0%
riscv_rv32im_instr_test	5	5	100.0%
riscv_user_mode_rand_test	10	10	100.0%
riscv_umode_tw_test	10	10	100.0%
riscv_invalid_csr_test	10	10	100.0%
riscv_pmp_basic_test	50	50	100.0%
riscv_pmp_disable_all_regions_test	50	50	100.0%
riscv_pmp_out_of_bounds_test	46	50	92.0%
riscv_pmp_full_random_test	577	600	96.2%
riscv_pmp_region_exec_test	20	20	100.0%
riscv_epmp_mml_test	20	20	100.0%
riscv_epmp_mml_execute_only_test	20	20	100.0%
riscv_epmp_mml_read_only_test	20	20	100.0%
riscv_epmp_mmwp_test	17	20	85.0%
riscv_epmp_rlb_test	20	20	100.0%
riscv_bitmanip_otearlgrey_test	10	10	100.0%
riscv_bitmanip_balanced_test	10	10	100.0%
riscv_debug_triggers_test	0	5	0.0%
Total	1457	1530	95.2%

Coverage

Functional	Block	Branch	Statement	Expression	Toggle	FSM	Assertion
89.7%	94.9%	88.7%	95.9%	90.5%	92.1%	100.0%	98.7%