sv-tests §[12.4.2](https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+12.4.2+priority_if) and §[12.5.3](https://chipsalliance.github.io/sv-tests-results/?v=circt_verilog+12.5.3+priority_case). As stated in the title, qualifiers are ignored in the generated Moore IR. These qualifiers are used to perform violation checks during simulation and provide optimization opportunities for synthesis.
sv-tests §12.4.2 and §12.5.3.
As stated in the title, qualifiers are ignored in the generated Moore IR.
These qualifiers are used to perform violation checks during simulation and provide optimization opportunities for synthesis.