Big update

.github/workflows/ci.yml

@@ -25,14 +25,17 @@ jobs:
           sudo mkdir /opt/riscv
           sudo tar -xzf riscv32-unknown-elf.gcc-12.1.0.tar.gz -C /opt/riscv/
           rm  riscv32-unknown-elf.gcc-12.1.0.tar.gz
+          root=$(pwd)
           echo "PATH=$PATH:/opt/riscv/bin" >> $GITHUB_ENV
-      - name: Build InterPRET
+          echo "FLEXPRET_ROOT_DIR=$root/flexpret" >> $GITHUB_ENV
+          echo "INTERPRET_ROOT_DIR=$root" >> $GITHUB_ENV
+      - name: Build and test FlexPRET
+        run : |
+          cd $FLEXPRET_ROOT_DIR
+          make clean && make emulator
+          make test
+      - name: Build and test InterPRET
         run: |
           make emulator N_CORES=4 THREADS=4 FLEX=false TRACE=0
-          root=$(pwd)
-          echo "PATH=$PATH:$root/flexpret/scripts/c:$root/emulator:$root/programs/scripts" >> $GITHUB_ENV
-          echo "FP_ROOT=$root" >> $GITHUB_ENV
-      - name: Run unit-tests
-        run: make unit-tests
-      - name: Run integration tests
-        run: make integration-tests
+          make unit-tests
+          make integration-tests

.gitignore

@@ -1,11 +1,14 @@
 .bsp/
 .metals/
+.idea/
 .vscode/
 project/
 target/
 build/
 emulator/*.v
 emulator/obj_dir
+emulator/ip-emu
+emulator/ip-verilator
 .bloop
 
 # Generated files
@@ -17,7 +20,6 @@ emulator/obj_dir
 **/*.map
 **/*.orig
 **/*.dump
-**/fp-emu
 **/*.fir
 **/*.app
 **/*.binary.txt

Makefile

@@ -6,8 +6,6 @@ SCRIPTS_DIR = flexpret/scripts
 BUILD_DIR = build
 RESOURCE_DIR = flexpret/src/main/resources
 
-
-
 # Compiler options.
 CXX = g++
 CXXFLAGS = -g -O2
@@ -44,7 +42,7 @@ verilog_raw: $(VERILOG_RAW)
 
 # --no-dedup flag is to make it possible to load programs directly into the ISpms
 $(VERILOG_RAW): 
-	sbt 'run $(CORE_CONFIG) $(SOC_CONFIG) --no-dedup --target-dir $(BUILD_DIR)'
+	sbt 'run verilator $(CORE_CONFIG) $(SOC_CONFIG) --no-dedup --target-dir $(BUILD_DIR)'
 
 # FPGA Verilog generation
 # FPGA_SRC_DIR = $(FPGA_DIR)/generated-$(CORE_CONFIG)

Makefrag

@@ -0,0 +1,23 @@
+ifndef FLEXPRET_ROOT_DIR
+$(error FLEXPRET_ROOT_DIR is not set. Please source env.bash)
+endif
+
+ifndef INTERPRET_ROOT_DIR
+$(error INTERPRET_ROOT_DIR is not set. Please source env.bash)
+endif
+
+EMU:=$(INTERPRET_ROOT_DIR)/emulator/ip-emu
+
+ifdef BOOTLOADER
+LINKER_SCRIPT := $(FLEXPRET_ROOT_DIR)/programs/lib/linker/flexpret_btl.ld	
+endif
+
+ifdef APP
+LINKER_SCRIPT := $(FLEXPRET_ROOT_DIR)/programs/lib/linker/flexpret_app.ld	
+endif
+
+include $(INTERPRET_ROOT_DIR)/lib/Makefrag
+
+
+app: compile
+	$(INTERPRET_ROOT_DIR)/programs/scripts/serialize_app.py $(NAME).mem $(NAME).app

README.md

@@ -7,7 +7,7 @@ InterPRET is a multicore FlexPRET architecture that uses a time-predictable Netw
 ### Prerequisites
 1. Verilator
 2. SBT
-3. RISCV 32-bit toolchain
+3. RISCV toolchain on the PATH. Download prebuild [rv32i-4.0.0](https://github.com/stnolting/riscv-gcc-prebuilt)
 
 ### Clone repo and set up 
 ```
@@ -19,7 +19,7 @@ source env.bash
 
 ### Build and run tests
 ```
-make tests
+make test
 ```
 The final tests, which consist of bootloading an application over serial might take a few minutes to complete.
 

build.sbt

@@ -1,23 +1,24 @@
+ThisBuild / scalaVersion     := "2.12.10"
+ThisBuild / version          := "0.1.0"
+ThisBuild / organization     := "PRETIS"
 
-
-val chiselVersion = "3.5.5"
+val chiselVersion = "3.5.6"
 
 lazy val interpret = (project in file("."))
   .settings(
     name := "interpret",
     libraryDependencies ++= Seq(
       "edu.berkeley.cs" %% "chisel3" % chiselVersion,
-      "edu.berkeley.cs" %% "chiseltest" % "0.5.5",
+      "edu.berkeley.cs" %% "chiseltest" % "0.5.6" % "test"
+    ),
+    scalacOptions ++= Seq(
+      "-language:reflectiveCalls",
+      "-deprecation",
+      "-feature",
+      "-Xcheckinit",
+      "-P:chiselplugin:genBundleElements",
     ),
-scalaVersion := "2.12.10", // Issue on scalamacros:paradise
-scalacOptions ++= Seq(
-  "-deprecation",
-  "-feature",
-  "-unchecked",
-  "-language:reflectiveCalls",
-),
-addCompilerPlugin("edu.berkeley.cs" %% "chisel3-plugin" % chiselVersion cross CrossVersion.full),
-addCompilerPlugin("org.scalamacros" %% "paradise" % "2.1.0" cross CrossVersion.full)
+    addCompilerPlugin("edu.berkeley.cs" % "chisel3-plugin" % chiselVersion cross CrossVersion.full),
   ).dependsOn(flexpret,soc_comm)
 
 // Import flexpret

emulator/emulator.mk

@@ -3,25 +3,10 @@
 # Edward Wang <edwardw@eecs.berkeley.edu>
 # Shaokai Lin <shaokai@berkeley.edu>
 
-EMULATOR_BIN = $(EMULATOR_DIR)/fp-emu
-HDL_SCRIPTS = $(SCRIPTS_DIR)/hdl
-TRACE ?= 0
+EMULATOR_BIN = $(EMULATOR_DIR)/ip-verilator
 
-$(EMULATOR_BIN): $(VERILOG_RAW) $(EMULATOR_DIR)/main.cpp $(EMULATOR_DIR)/uartsim.cpp $(HDL_SCRIPTS)/simify_verilog.py
-	# Inject the right simulation constructs
-	# FIXME: Remove this alltogether, currently only used for  enabling tracing
+$(EMULATOR_BIN): $(VERILOG_RAW) $(EMULATOR_DIR)/main.cpp $(EMULATOR_DIR)/uartsim.cpp
 	cp $(RESOURCE_DIR)/DualPortBram.v $(EMULATOR_DIR)/DualPortBram.v
-ifeq ($(TRACE),1)
-	@echo "Enabling tracing on Verilator"
-	$(HDL_SCRIPTS)/simify_verilog.py $(VERILOG_RAW) > $(EMULATOR_DIR)/$(MODULE).sim.v
-	(cd $(EMULATOR_DIR) && verilator --cc $(MODULE).sim.v --timescale 1ns/1ns --exe --trace --build main.cpp uartsim.cpp)
-else
-	@echo "Disabling tracing on Verilator"
 	cp $(VERILOG_RAW) $(EMULATOR_DIR)/$(MODULE).sim.v
-	(cd $(EMULATOR_DIR) && verilator --cc $(MODULE).sim.v --timescale 1ns/1ns --exe --build main.cpp uartsim.cpp)
-endif
-
-
+	(cd $(EMULATOR_DIR) && verilator --cc $(MODULE).sim.v --timescale 1ns/1ns --exe --trace --build main.cpp uartsim.cpp)
 	cp $(EMULATOR_DIR)/obj_dir/V$(MODULE) $(EMULATOR_BIN)
-
-	echo "Emulator usage: Run '$(EMULATOR_BIN)'. The emulator expects to find the program for each core stored in the directory it is invoked from with the names 'core1.mem', 'core2.mem', 'coreN.mem' etc. The programs can be built using 'scripts/c/riscv_build.sh coreN <C files...>'. The emulation will generate a VCD called 'trace.vcd'. Use flexpret_io.h to print or to terminate simulation."

emulator/ip-emu

@@ -0,0 +1,39 @@
+#!/bin/bash
+# Simple wrapper around the ip-verilator emulation
+
+# Get the directory of the script and the verilator emulation
+script_dir=$(dirname "$0")
+script_name=$(basename "$0")
+emu="$script_dir/ip-verilator"
+working_dir=$(pwd)
+
+echo "Running InterPRET emulator:"
+
+# Check if exactly one argument is provided
+if [ $# -lt 1 ]; then
+  echo "Usage: $script_name ispm-file [uart_file] [--trace]"
+  exit 1
+fi
+
+# Check if the file exists
+if [ ! -f "$1" ]; then
+  echo "File not found: $1"
+  exit 1
+fi
+
+# Check if the file exists
+if [ ! -f "$emu" ]; then
+  echo "Did not find verilator emulator at: $emu"
+  exit 1
+fi
+
+# Get the filename from the path
+filename=$(basename "$1")
+
+# Copy the file to the current directory
+cp "$1" "$working_dir/ispm.mem"
+
+# Excute the verilator emulation
+echo "${@:2}"
+"$script_dir/ip-verilator" "${@:2}"
+

emulator/main.cpp

@@ -6,6 +6,8 @@
  */
 #include "VTop.h"
 #include "verilated.h"
+#include "verilated_vcd_c.h"
+#include <iostream>
 #include "uartsim.h"
 
 uint64_t timestamp = 0;
@@ -16,13 +18,56 @@ double sc_time_stamp() {
 
 int main(int argc, char* argv[]) {
   Verilated::commandArgs(argc, argv);
-  Verilated::traceEverOn(true);
+  bool trace_enabled = false;
+  bool uart_file = false;
+  int uart_file_argv = 0;
+
+  // We accept 2 optional command line args, in arbitrary order
+  // A) `--trace` to turn on VCD tracing
+  // B) file_path.bin to a binary file which will be read into the uart rx pin of the InterPRET
+
+  if (argc == 2) {
+    if (!strcmp(argv[1], "--trace")) {
+      std::cout << "Tracing enabled" << std::endl;
+      trace_enabled = true;
+      Verilated::traceEverOn(true);
+    } else {
+      uart_file = true;
+      uart_file_argv = 1;
+    }
+  }
+
+  if (argc == 3) {
+    uart_file = true;
+    if (!strcmp(argv[1], "--trace")) {
+      std::cout << "Tracing enabled" << std::endl;
+      trace_enabled = true;
+      Verilated::traceEverOn(true);
+      uart_file_argv = 2;
+    } else if (argv[2], "--trace") {
+      std::cout << "Tracing enabled" << std::endl;
+      trace_enabled = true;
+      Verilated::traceEverOn(true);
+      uart_file_argv = 1;
+    } else {
+      std::cout << "Dont recognize command line arguments:" <<argv[1] <<"," <<argv[2] <<std::endl;
+      std::cout << "Usage ip-verilator [uart_file] [--trace]" <<std::endl;
+      exit(1);
+    }
+  }
 
 
   VTop* top = new VTop;
+  VerilatedVcdC *trace;
+  if (trace_enabled) {
+    trace = new VerilatedVcdC;
+    top->trace(trace, 99);
+    trace->open("trace.vcd");
+  }
 
-  if (argc == 2) {
-    uartsim_init(argv[1]);
+  if (uart_file) {
+    std::cout <<"Passing in uart_file: `" <<argv[uart_file_argv] <<"`" <<std::endl;
+    uartsim_init(argv[uart_file_argv]);
   } else {
     uartsim_init("");
   }
@@ -35,13 +80,33 @@ int main(int argc, char* argv[]) {
     top->clock = 1;
     top->eval();
     timestamp+=1;
+
+    if (trace_enabled) {
+      trace->dump(10*timestamp);
+    }
+
     if (timestamp > 10) {
-      uartsim_print_rx( (int *) &top->io_gpio_out_1, 0);
+      uartsim_print_rx( (int *) &top->io_uart_tx, 0);
       uartsim_write(&top->io_uart_rx);
     }
     top->clock = 0;
     top->eval();
     timestamp+=1;
+
+    if (trace_enabled) {
+      trace->dump(10*timestamp);
+      trace->flush();
+    }
+
+    if (top->io_stop) {
+      std::cout <<"Verilator received stop signal from InterPRET" <<std::endl;
+      break;
+    }
+  }
+
+  if (trace_enabled) {
+    trace->close();
+    delete trace;
   }
 
   delete top;

env.bash

@@ -1,9 +1,5 @@
-export FP_ROOT=$(pwd)
+export INTERPRET_ROOT_DIR=$(pwd)
+export FLEXPRET_ROOT_DIR=$INTERPRET_ROOT_DIR/flexpret
 
-# Put riscv gcc compiler on the path
-# export PATH="$PATH:/opt/riscv32/bin"
-
-# Put riscv_compile.sh and riscv_clean.sh on the path
-export PATH="$PATH:$FP_ROOT/flexpret/scripts/c"
 # Put the generated emulator on the path
-export PATH="$PATH:$FP_ROOT/emulator"
+export PATH="$PATH:$INTERPRET_ROOT_DIR/emulator"

env.fish

@@ -1,6 +1,4 @@
-set -Ux FP_ROOT (pwd)
+set -Ux INTERPRET_ROOT_DIR (pwd)
+set -Ux FLEXPRET_ROOT_DIR $INTERPRET_ROOT_DIR/flexpret
 
-set PATH $PATH:/opt/riscv32/bin
-set PATH $PATH:$FP_ROOT/flexpret/scripts/c
-set PATH $PATH:$FP_ROOT/emulator
-set PATH $PATH:$FP_ROOT/programs/scripts
+set PATH $PATH:$INTERPRET_ROOT_DIR/emulator

lib/Makefrag

@@ -0,0 +1,14 @@
+
+IP_LIB_DIR=$(INTERPRET_ROOT_DIR)/lib
+ifdef BOOTLOADER
+LIB_SOURCES += \
+    $(IP_LIB_DIR)/interpret_uart.c \
+    $(IP_LIB_DIR)/interpret_wb.c
+else
+LIB_SOURCES += \
+    $(IP_LIB_DIR)/interpret_noc.c \
+    $(IP_LIB_DIR)/interpret_uart.c \
+    $(IP_LIB_DIR)/interpret_wb.c \
+    $(IP_LIB_DIR)/interpret_stdio.c
+endif
+LIB_INCS += -I$(IP_LIB_DIR)/include

lib/include/interpret.h

@@ -0,0 +1,10 @@
+#ifndef INTERPRET_H
+#define INTERPRET_H
+
+#include "flexpret.h"
+#include "interpret_wb.h"
+#include "interpret_uart.h"
+#include "interpret_stdio.h"
+#include "interpret_noc.h"
+
+#endif