GitHub - krishkc5/dram_vlsi: Design and optimization of a 16x4 DRAM subsystem implemented in a 45 nm VLSI process. Contains schematics, simulations, and timing analysis supporting the complete dynamic memory architecture. Focus areas include cell topology, wordline/bitline drivers, sense-amplifier behavior, refresh considerations, and tradeoffs across area, power, and delay.

Branches Tags

Name		Name	Last commit message	Last commit date
Latest commit History 11 Commits
16x4_DRAM		16x4_DRAM
1T1C_bitcell		1T1C_bitcell
BL_precharge		BL_precharge
NAND2		NAND2
NOR2		NOR2
clk_gen		clk_gen
min_buffer		min_buffer
min_inv		min_inv
sense_amp		sense_amp
testbench_1T1C_bitcell/schematic		testbench_1T1C_bitcell/schematic
testbench_BL_precharge/schematic		testbench_BL_precharge/schematic
testbench_clk_gen/schematic		testbench_clk_gen/schematic
testbench_sense_amp/schematic		testbench_sense_amp/schematic
tri_buffer		tri_buffer
writeup		writeup
.oalib		.oalib
cdsinfo.tag		cdsinfo.tag
data.dm		data.dm

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Design and optimization of a 16x4 DRAM subsystem implemented in a 45 nm VLSI process. Contains schematics, simulations, and timing analysis supporting the complete dynamic memory architecture. Focus areas include cell topology, wordline/bitline drivers, sense-amplifier behavior, refresh considerations, and tradeoffs across area, power, and delay.