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ENGG-3380-final-project
ENGG-3380-final-project PublicA 16 Bit Processor designed using VHDL and simulated on Vivado, that can perform R, I and J type instructions.
VHDL
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release-ops-manager
release-ops-manager PublicManage and automate team releases with a web UI, REST API, and repeatable DevOps pipelines; includes Docker images, build scripts, and Ansible playbooks
Java
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