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2 changes: 1 addition & 1 deletion par.yml
Original file line number Diff line number Diff line change
Expand Up @@ -158,4 +158,4 @@ par.innovus.use_cco: true
# All the placement constraints specified above will be ignored.
# This might lead to poor QoR and more DRVs.

#par.innovus.floorplan_mode: auto
#par.innovus.floorplan_mode: auto
1 change: 1 addition & 0 deletions src/ALU.v
Original file line number Diff line number Diff line change
Expand Up @@ -17,6 +17,7 @@ module ALU(
output reg [31:0] Out
);

initial Out = 32'd0;
// Implement your ALU here, then delete this comment
always @(*) begin
case (ALUop)
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1 change: 1 addition & 0 deletions src/ALUdec.v
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,7 @@ module ALUdec(
output reg [3:0] ALUop
);

initial ALUop = 4'd0;
// Implement your ALU decoder here, then delete this comment
always @(*) begin
case (opcode)
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1 change: 1 addition & 0 deletions src/ASel.v
Original file line number Diff line number Diff line change
Expand Up @@ -15,6 +15,7 @@ assign funct3 = inst[14:12];
wire uses_pc;
assign uses_pc = (opcode == `OPC_AUIPC || opcode == `OPC_JAL || opcode == `OPC_BRANCH)? 1'b1: 1'b0;

initial ASelSignal = 1'b0;
always @(*) begin
case (uses_pc)
1'b1: ASelSignal = 1'b1;
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2 changes: 2 additions & 0 deletions src/Adder.v
Original file line number Diff line number Diff line change
Expand Up @@ -9,6 +9,8 @@ module Adder (
output reg [31:0] stage1_pc4
);

initial stage1_pc4 = stage1_pc + 32'd4;

always @(*) begin
case (PCAddSelect)
2'b01: stage1_pc4 = stage1_pc + stage1_imm;
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2 changes: 2 additions & 0 deletions src/BSel.v
Original file line number Diff line number Diff line change
Expand Up @@ -16,6 +16,8 @@ assign funct3 = inst[14:12];
wire uses_imm;
assign uses_imm = (opcode == `OPC_ARI_ITYPE || opcode == `OPC_LUI || opcode == `OPC_AUIPC || opcode == `OPC_JAL || opcode == `OPC_JALR || opcode == `OPC_BRANCH || opcode == `OPC_STORE || opcode == `OPC_LOAD || opcode == `OPC_CSR)? 1'b1: 1'b0;

initial BSelSignal = 1'b0;

always @(*) begin
case (uses_imm)
1'b1: BSelSignal = 1'b1;
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6 changes: 4 additions & 2 deletions src/BrUn.v
Original file line number Diff line number Diff line change
Expand Up @@ -8,6 +8,8 @@ module BrUn (
wire [6:0] opcode = inst[6:0];
wire [2:0] funct3 = inst[14:12];

initial BrUnSignal = 1'b0;

always @(*) begin
case(opcode)
`OPC_BRANCH: begin
Expand All @@ -16,10 +18,10 @@ always @(*) begin
`FNC_BGEU: BrUnSignal = 1'b1;
`FNC_BLT: BrUnSignal = 1'b0;
`FNC_BGE: BrUnSignal = 1'b0;
default: BrUnSignal = 1'bx;
default: BrUnSignal = 1'b0;
endcase
end
default: BrUnSignal = 1'bx;
default: BrUnSignal = 1'b0;
endcase
end

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