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IOb-TIMER

IOb-TIMER is 64-bit hardware timer peripheral, equipped with reset, enable and reading functions. It includes a software direver and an example C application.

Clone the repository

git clone --recursive git@github.com:IObundle/iob-timer.git

Simulation

To simulate:

make sim

To visualise simulation waveforms

make sim-waves

clean simulation files:

make sim-clean

FPGA

To compile the FPGA:

make fpga

To clean FPGA files:

make fpga-clean

or to clean and delete 3rd party IP:

make fpga-clean-ip

Documentation

To compile the chosen document type:

make doc [DOC_TYPE=[**pb**|ug]]

To clean document files:

make doc-clean

To clean document files including pdf files:

make doc-pdfclean

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Simple Timer IP Core in Verilog

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  • TeX 27.5%
  • Makefile 27.1%
  • C 15.5%
  • Verilog 14.3%
  • Tcl 10.7%
  • Shell 4.4%
  • SystemVerilog 0.5%