Modular inference system based on a KNN model on configurable logic for hardware acceleration
This project aims to accelerate one of the microprocessors availables on the configurable device (Intel Altera Cyclone V FPGA), with which it will interact through the AXI4 Lite protocol. The system is modular in terms of the number of neighbours to consider, the number of input dimensions, and the number of vectors that the configurable device will store. The training vector is stored in an externa SDRAM memory.
The project can be built using HDL software such as Vivado or Quartus. The makefile can be used to build and test the project if the user have Icarus Verilog and Surfer Waveform Viewer installed.
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`make all´: Build the project with Icarus Verilog and show waveforms on Surfer Viewer.
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`make run´: Build the project with Icarus Verilog.
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`make clean´: Remove files from the building process.