PTA: Add chip to outputs and estimate signal-to-clutter ratio.

[Tyler-g-hudson]

This PR adds the PTA chip as a PTA output, and incorporates a method of calculating signal-to-clutter (SCR) ratio in dB. This value would be useful for populating error bars in PTA trending.

[Tyler-g-hudson]

This is a new calculation for me, so I'd like for folks to read carefully over the code and let me know if I've done anything wrong.

@bhawkins There was a point where you said that the peak power and clutter power should be multiplied by the resolution area - these terms canceled out when calculating the ratio so I removed them to simplify the code. Let me know if I have done this in error.

[Tyler-g-hudson]

@nemo794 This is the PR I was discussing with you earlier today.

[JensReimann]

Skipping the multiplication with resolution area should be okay. It cancels as you correctly stated. The ratio in 1014 must be unitless.

[rad-eng-59]

The methodology can be improved with more flexibility by doing the following, IMO.

Baseband RSLC within the 2-D chirp in both direction and get the Range/AZ impulse response as we normally do for PTA analysis. Then, multiply the two response to create 2-D response. Do a proper peak normalization by using peak of 2-D impulse response assuming SNR>>10 dB.
Finally, subtract that deterministic non-random signal from chip box and calculate variance (not sum of square of samples!) over 2-D residual within chip given random clutter/background noise.
This will give you clutter plus additive noise not just clutter.
Note that the assumption here is that CR impulse response is non-random that affects the DC in both range and AZ over the 2-D chip while the clutter+noise is random with zero mean but some non-zero variance that you are after.

No need to define clutter_half_chip or check for boundaries. The hidden assumption here is that background clutter for any chip size whether it is centered around CR or not, are pretty homogeneous.

Edit: Alternatively, perform EVD with rank equals to half of chip length (or less but larger than 4) and find min Eigen value to represent clutter+noise power.

[rad-eng-59]

Wouldn't it be better to define it as fraction of the half input chip size?
Or alternatively, set the default to None and determine its value based on input chip rather than setting it to absolute value which may not work for smaller chirp size than 32.

[Tyler-g-hudson]

This is something I hoped to discuss in PR review - my understanding of the push-and-pull affecting this parameter is that it should be wide enough to capture a reasonable cross-section of the clutter while not being so large that it captures terrain-related variation in magnitude, per an offline discussion with @bhawkins.

With the above having been said, it's not obvious to me that varying SCR estimation chip size by the broader PTA chip is the right method unless the PTA chip is pretty small relative to the optimal SCR estimation chip, which makes this analysis harder to do in general.

Maybe the better option is to acquire this chip from the SLC instead of the PTA chip, using the known offsets from PTA to select a clutter estimation chip directly from the SLC so we don't have to worry about edge cases like when the PTA chip is small.

[JensReimann]

The methodology can be improved with more flexibility by doing the following, IMO.

Baseband RSLC within the 2-D chirp in both direction and get the Range/AZ impulse response as we normally do for PTA analysis. Then, multiply the two response to create 2-D response. Do a proper peak normalization by using peak of 2-D impulse response assuming SNR>>10 dB. Finally, subtract that deterministic non-random signal from chip box and calculate variance (not sum of square of samples!) over 2-D residual within chip given random clutter/background noise. This will give you clutter plus additive noise not just clutter. Note that the assumption here is that CR impulse response is non-random that affects the DC in both range and AZ over the 2-D chip while the clutter+noise is random with zero mean but some non-zero variance that you are after.

No need to define clutter_half_chip or check for boundaries. The hidden assumption here is that background clutter for any chip size whether it is centered around CR or not, are pretty homogeneous.

Edit: Alternatively, perform EVD with rank equals to half of chip length (or less but larger than 4) and find min Eigen value to represent clutter+noise power.

I'm not sure about the approach you described above. The main assumption of the current approach is that the clutter is homogeneous in the region around the target. This assumption is made whenever statistics (e.g. the mean value) are used to calculate the clutter contribution.
Canceling the target response only improves the situtation as it increases the number of samples used for the statistic. However, the estimate may deteriorate if not all of the target energy is canceled, i.e., due to ionospheric effects like scintillation.

One alternative is a non-statistical approach in which the clutter at the pixels with the maximum magnitude is estimated, and then the signal-to-clutter ratio is calculated using those pixels. However, I am concerned that the clutter estimation will be contaminated by the remaining target energy, especially since it is in a region of the IRF with high SCR, where a significant amount of energy must be canceled.